IP Library Granted Patent US 7,170,134
Granted Patent B2
US 7,170,134 · App. 10/994,358 · Granted Jan 30, 2007

Semiconductor device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,170,134
App. No.
10/994,358
Granted
Jan 30, 2007
Kind
B2
Abstract

P-type buried regions 104 a and 104 b are formed in an extended drain region 102 formed in a P-type semiconductor substrate 110 . An N-type buried region 113 is formed between the P-type buried regions 104 a and 104 b . An N-type impurity concentration of the N-type buried region 113 along a G–G′ plane is low in the vicinity of boundaries between the N-type buried region 113 and the P-type buried regions 104 a and 104 b and is increased from the boundaries to an inside of the N-type buried region 113.

Claims (14)

1. A lateral semiconductor device, comprising:

a first conductivity type semiconductor substrate;

a second conductivity type source region formed in the semiconductor substrate;

a second conductivity type extended drain region formed in the semiconductor substrate;

a gate electrode formed over the semiconductor substrate between the source region and the extended drain region;

a drain region formed in the extended drain region and having a second conductivity type impurity concentration higher than that of the extended drain region;

at least two first conductivity type buried regions formed in the extended drain region at different depths from a surface of the extended drain region; and

a second conductivity type buried region formed between the first conductivity type buried regions,

wherein a second conductivity type impurity concentration at an inside of the second conductivity type buried region is higher than a second conductivity type impurity concentration at boundaries between the first conductivity type buried regions and the second conductivity type buried region.

2. The semiconductor device according to claim 1 , wherein a highest second conductivity type impurity concentration of the second conductivity type buried region formed at a most shallow position from the surface of the extended drain region is higher than a second conductivity type impurity concentration at the surface of the extended drain region.

3. The semiconductor device according to claim 1 , wherein the first conductivity type buried region is formed by ion implantation.

4. The semiconductor device according to claim 1 , wherein the second conductivity type buried region is formed by ion implantation.

5. The semiconductor device according to claim 1 , wherein the second conductivity type buried region is electrically connected to the semiconductor substrate.

6. The semiconductor device according to claim 1 , wherein the first conductivity type buried region and the second conductivity type buried region have substantially the same planar shape.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 26, 2014
From: PANASONIC CORPORATION
To: COLLABO INNOVATIONS, INC.
Reel/Frame 033021/0806 →
LIEN Recorded Jan 13, 2014
From: COLLABO INNOVATIONS, INC.
To: PANASONIC CORPORATION
Reel/Frame 031997/0445 →
CHANGE OF NAME Recorded Jan 8, 2014
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 031947/0358 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 23, 2004
From: TAKEHANA, YASUHIRO; UNO, TOSHIHIKO
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 016027/0640 →