There is provided a memory device which has a refresh control circuit generating a refresh command internally; a refresh interrupt control circuit generating a refresh interrupt signal for accepting the refresh command for a predetermined period when a write command is inputted externally; a command decoder instructing, when a write command is inputted externally, a writing operation after a refresh command accepting period by the refresh interrupt signal finishes and after waiting a refreshing operation to finish if the refreshing operation is being performed; and a comparing circuit instructing a refreshing operation when the refresh command is generated during the refresh command accepting period by the refresh interrupt signal.
1. A memory device, comprising:
a refresh control circuit generating a refresh command internally;
a refresh interrupt control circuit generating a refresh interrupt signal for accepting the refresh command for a certain period when a write command is inputted externally;
a command decoder instructing, when a write command is inputted externally, a writing operation after a refresh command accepting period by the refresh interrupt signal finishes and after waiting a refreshing operation to finish if the refreshing operation is being performed; and
a comparing circuit instructing a refreshing operation when the refresh command is generated during the refresh command accepting period by the refresh interrupt signal.
2. The memory device according to claim 1 ,
wherein said command decoder instructs, when a read command is inputted externally, a reading operation with priority even if the refresh command is generated thereafter, and
wherein said comparing circuit instructs the refreshing operation after the reading operation finishes.
3. The memory device according to claim 1 ,
wherein the write command is inputted after an output disable command.
4. The memory device according to claim 1 ,
wherein the write command is inputted when not being in an output disable state.
5. The memory device according to claim 3 ,
wherein said comparing circuit makes a refreshing operation to wait when the refresh command is generated in a period from inputting the output disable command to inputting the write command.
6. The memory device according to claim 1 ,
wherein said refresh control circuit periodically generates the refresh command.
7. The memory device according to claim 1 , further comprising:
a memory cell configured to perform a writing operation and a refreshing operation according to the write command and the refresh command.
8. The memory device according to claim 2 ,
wherein said command decoder instructs the reading operation after the read command is inputted and a certain period passes so that an address is determined.
9. The memory device according to claim 2 ,
wherein said refresh control circuit periodically generates the refresh command.
10. The memory device according to claim 9 , further comprising:
a memory cell configured to perform a writing operation and a refreshing operation according to the write command and the refresh command.
11. The memory device according to claim 10 ,
wherein said command decoder instructs the writing operation after the write command is inputted and a certain period passes so that an address is determined.
12. The memory device according to claim 11 ,
wherein the write command is inputted after an output disable command.
13. The memory device according to claim 11 ,
wherein the write command is inputted when not being in an output disable state.
14. The memory device according to claim 12 ,
wherein said comparing circuit makes a refreshing operation to wait when the refresh command is generated in a period from inputting the output disable command to inputting the write command.