Bias circuit having transistors that selectively provide current that controls generation of bias voltage

1. A bias circuit which generates a bias voltage, comprising:

a first MOS transistor coupled between a first reference voltage terminal and a voltage dividing node, wherein the first MOS transistor has a first ON-state resistance;

a second MOS transistor coupled in parallel with the first MOS transistor, wherein the second MOS transistor has a second ON-state resistance which is lower than the first ON-state resistance of the first MOS transistor;

a resistance circuit coupled between the voltage dividing node and a second reference voltage terminal; and

a voltage generator coupled with the voltage dividing node, the voltage generator outputting the bias voltage in dependence upon an electrical potential on the voltage dividing node,

wherein the first and second control signals turn ON the first and second MOS transistors before the voltage generator outputs the bias voltage, and wherein the first control signal turns ON the first MOS transistor and the second control signal turns OFF the second MOS transistor after the voltage generator outputs the bias voltage.

2. The bias circuit according to claim 1 , further comprising:

a two-terminal circuit element having a PN-junction which is coupled between the voltage dividing node and the voltage generator;

wherein the voltage generator outputs the bias voltage in accordance with a voltage across the two-terminal circuit element.

3. The bias circuit according to claim 2 , wherein the two-terminal circuit element is a diode-connected MOS transistor.

4. The bias circuit according to claim 1 , wherein the voltage generator is controlled by the first control signal.

5. The bias circuit according to claim 1 , wherein the first control signal is a standby signal.

6. The bias circuit according to claim 1 , wherein the resistance circuit is a constant-voltage circuit.

7. The bias circuit according to claim 1 , wherein the voltage generator comprises:

an output terminal from which the bias voltage is output;

a first current mirror circuit coupled between the first reference voltage terminal and the output terminal, wherein the first current mirror circuit comprises two P-type MOS transistors; and

a second current mirror circuit coupled between the output terminal and the second reference voltage terminal, wherein the second current mirror circuit comprises two N-type MOS transistors.

8. The bias circuit according to claim 1 , wherein a conductive type of the first MOS transistor is the same as that of the second MOS transistor.

9. The bias circuit according to claim 1 , further comprising:

a third MOS transistor coupled between the voltage dividing node and the second reference voltage terminal, wherein a conductive type of the third MOS transistor is different from that of the second MOS transistor.

10. The bias circuit according to claim 9 , wherein the third MOS transistor has a third ON-state resistance which is lower than the first ON-state resistance of the first MOS transistor.

11. The bias circuit according to claim 9 , wherein the third MOS transistor is turned ON when the second MOS transistor is turned OFF.

12. The bias circuit according to claim 9 , wherein the third MOS transistor is turned ON when the first MOS transistor is turned OFF.

13. The bias circuit according to claim 1 , wherein the electrical potential on the voltage dividing node is generated based on an electrical current passing through the first and second MOS transistors and the resistance circuit.

14. The bias circuit according to claim 1 , wherein the first reference voltage terminal receives a power supply voltage and the second reference voltage terminal receives a ground voltage.

15. The bias circuit according to claim 1 , wherein the first ON-state resistance allows a current of at least 5 μA to pass through the first MOS transistor.

16. A bias circuit which generates a bias voltage, comprising:

a first MOS transistor coupled between a first reference voltage terminal and a voltage dividing node, wherein the first MOS transistor has a first gate width and a first gate length:

a second MOS transistor coupled in parallel with the first MOS transistor, wherein the second MOS transistor has a second gate width and a second gate length, and wherein a ratio of the second gate width to the second gate length is greater than a ratio of the first gate width to the first gate length;

a resistance circuit coupled between the voltage dividing node and the second reference voltage terminal; and

a voltage generator coupled with the voltage dividing node, the voltage generator outputting the bias voltage in dependence upon an electrical potential on the voltage dividing node,

wherein the first and second control signals turn ON the first and second MOS transistors before the voltage generator outputs the bias voltage, and wherein the first control signal turns ON the first MOS transistor and the second control signal turns OFF the second MOS transistor after the voltage generator outputs the bias voltage.

17. The bias circuit according to claim 16 , further comprising:

a PN-junction circuit which is coupled between the voltage dividing node and the voltage generator;

wherein the voltage generator outputs the bias voltage in accordance with a voltage across the PN-junction circuit.

18. The bias circuit according to claim 17 , wherein the PN-junction circuit is a diode-connected MOS transistor.

19. The bias circuit according to claim 16 , wherein the voltage generator is controlled by the first control signal.

20. The bias circuit according to claim 16 , wherein the first control signal is a standby signal.

21. The bias circuit according to claim 16 , wherein the resistance circuit is a constant-voltage circuit.

22. The bias circuit according to claim 16 , wherein the voltage generator comprises:

an output terminal from which the bias voltage is output;

a first current mirror circuit coupled between the first reference voltage terminal and the output terminal, wherein the first current mirror circuit comprises two P-type MOS transistors; and

a second current mirror circuit coupled between the output terminal and the second reference voltage terminal, wherein the second current mirror circuit comprises two N-type MOS transistors.

23. The bias circuit according to claim 16 , wherein a conductive type of the first MOS transistor is the same as that of the second MOS transistor.

24. The bias circuit according to claim 16 , further comprising:

a third MOS transistor coupled between the voltage dividing node and the second reference voltage terminal, wherein a conductive type of the third MOS transistor is different from that of the second MOS transistor.

25. The bias circuit according to claim 24 , wherein the third MOS transistor has a third gate width and a third gate length, a ratio of the third gate width to the third gate length being greater than the ratio of the first gate width to the first gate length.

26. The bias circuit according to claim 24 , wherein the third MOS transistor is turned ON when the second MOS transistor is turned OFF.

27. The bias circuit according to claim 24 , wherein the third MOS transistor is turned ON when the first MOS transistor is turned OFF.

28. The bias circuit according to claim 16 , wherein the electrical potential on the voltage dividing node is generated based on an electrical current passing through the first and second MOS transistors and the resistance circuit.

29. The bias circuit according to claim 16 , wherein the first reference voltage terminal receives a power supply voltage and the second reference voltage terminal receives a ground voltage.

30. The bias circuit according to claim 16 , wherein the first gate width and the first gate length allow a current of at least 5 μA to pass through the first MOS transistor.

31. A bias circuit which generates first and second bias voltages, comprising:

a first MOS transistor coupled between a first reference voltage terminal and a voltage dividing node, wherein the first MOS transistor is capable of passing a first ON-state current therethrough;

a second MOS transistor coupled in parallel with the first MOS transistor, wherein the second MOS transistor is capable of passing a second ON-state current therethrough, the second ON-state current being greater than the first ON-state current;

a resistance circuit coupled between the voltage dividing node and the second reference voltage terminal; and

a voltage generator coupled with the voltage dividing node, the voltage generator outputting the first and second bias voltages in dependence upon an electrical potential generated on the voltage dividing node,

wherein the first and second control signals turn ON the first and second MOS transistors before the voltage generator outputs the first and second bias voltages, and wherein the first control signal turns ON the first MOS transistor and the second control signal turns OFF the second MOS transistor after the voltage generator outputs the first and second bias voltages.

32. The bias circuit according to claim 31 , further comprising:

a diode which is coupled between the voltage dividing node and the reference voltage generator;

wherein the reference voltage generator outputs the first and second bias voltages in accordance with a voltage applied across the diode.

33. The bias circuit according to claim 32 , wherein the diode is a diode-connected MOS transistor.

34. The bias circuit according to claim 32 , wherein an amount of the first ON-state current is controlled by the first control signal and an amount of the second ON-state current is controlled by the second control signal.

35. The bias circuit according to claim 31 , wherein the voltage generator is controlled by the first control signal.

36. The bias circuit according to claim 31 , wherein the first control signal is a standby signal.

37. The bias circuit according to claim 31 , wherein the resistance circuit is a constant-voltage circuit.

38. The bias circuit according to claim 31 , wherein the voltage generator comprises:

first and second output terminals from which the first and second bias voltages are respectively output;

a first current mirror circuit coupled between the first reference voltage terminal and the first output terminal, wherein the first current mirror circuit comprises two P-type MOS transistors; and

a second current mirror circuit coupled between the second output terminal and the second reference voltage terminal, wherein the second current mirror circuit comprises two N-type MOS transistors.

39. The bias circuit according to claim 31 , wherein a conductive type of the first MOS transistor is the same as that of the second MOS transistor.

40. The bias circuit according to claim 31 , further comprising:

a third MOS transistor coupled between the voltage dividing node and the second reference voltage terminal, wherein a conductive type of the third MOS transistor is different from that of the second MOS transistor.

41. The bias circuit according to claim 40 , wherein the third MOS transistor can pass a third ON-state current therethrough, the third ON-state current being larger than the first ON-state current.

42. The bias circuit according to claim 40 , wherein the third MOS transistor is turned ON when the second MOS transistor is turned OFF.

43. The bias circuit according to claim 40 , wherein the third MOS transistor is turned ON when the first MOS transistor is turned OFF.

44. The bias circuit according to claim 31 , wherein the electrical potential on the voltage dividing node is generated based on an electrical current passing through the first and second MOS transistors and the resistance circuit.

45. The bias circuit according to claim 31 , wherein the first reference voltage terminal receives a power supply voltage and the second reference voltage terminal receives a ground voltage.

46. The bias circuit according to claim 31 , wherein the first ON-state current is equal to or more than 5 μA.