Programmable phase shift circuitry
View Patent ↗A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.
1. A clock circuit for outputting a clock signal, the clock circuit comprising:
a multiplexer having inputs coupled to first and second local signals of the clock circuit;
a variable impedance circuit coupled to the multiplexer and the output clock signal of the clock circuit, and having an input coupled to a control signal of the clock circuit, wherein the control signal is indicative of a phase difference between a reference clock signal and a feedback clock signal; and
a capacitance coupled to the variable impedance circuit.
2. The clock circuit of claim 1 further comprising at least one buffer circuit coupled between the variable impedance circuit and the output clock signal of the clock circuit.
3. The clock circuit of claim 1 further comprising at least one buffer circuit coupled between the multiplexer and the variable impedance circuit.
4. The clock circuit of claim 1 wherein the control signal is coupled to a phase detector circuit receiving the reference clock signal and the feedback clock signal.
5. The clock circuit of claim 1 wherein the impedance circuit comprises a first transistor whose gate is coupled to the control signal.
6. The clock circuit of claim 5 wherein:
the impedance circuit further comprises a second transistor;
the gate of the second transistor is coupled to the control signal; and
the source of the second transistor is coupled to the source of the first transistor.
7. The clock circuit of claim 6 wherein:
the impedance circuit further comprises a third transistor;
the source of the third transistor is coupled to the drain of the second transistor; and
the gate and drain of the third transistor are coupled to the drain of the first transistor.
8. A programmable logic device comprising the clock circuit of claim 1 .
9. A processing unit comprising the programmable logic device of claim 8 .
10. A method for generating an output clock signal, the method comprising:
generating a signal indicative of a phase difference between a reference clock signal and a feedback clock signal;
varying a control signal in response to receiving the signal indicative of the phase difference;
selecting a first signal or a second signal to provide a third signal using a multiplexer;
providing a delay to a fourth signal that is coupled to the third signal, wherein the delay is based on a capacitance;
varying the capacitance in response to the varying the control signal by varying an impedance of a variable impedance circuit; and
providing the output clock signal in response to providing the delay to the fourth signal.
11. The method of claim 10 wherein providing the output clock signal comprises:
accepting the delayed fourth signal as an input to at least one buffer circuit; and
generating the output clock signal from the at least one buffer circuit.
12. A method for generating at least one output clock signal, the method comprising:
generating a signal indicative of a phase difference between a reference clock signal and a feedback clock signal using a phase detector;
generating a control signal in response to receiving the signal indicative of the phase difference;
varying a delay of a first local signal in response to receiving the control signal, wherein the varying comprises adjusting a first capacitance by varying an impedance of a first variable impedance circuit coupled to the first local signal;
providing a first output clock signal in response to receiving the first local signal;
varying a delay of a second local signal in response to receiving the control signal, wherein the varying comprises adjusting a second capacitance by varying an impedance of a second variable impedance circuit coupled to the second local signal;
providing a second output clock signal in response to receiving the second local signal; and
selecting from among the first and second output signals to provide the feedback clock signal.