IP Library Granted Patent US 7,426,686
Granted Patent B2
US 7,426,686 · App. 10/996,825 · Granted Sep 16, 2008

System and method for verifying data integrity

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Quick Facts
Patent No.
US 7,426,686
App. No.
10/996,825
Granted
Sep 16, 2008
Kind
B2
Abstract

A system for verifying data integrity includes a central processing unit (CPU) ( 1 ), a non-volatile random access memory (NVRAM) ( 2 ), and a program memory ( 3 ). The NVRAM includes: a plurality of data blocks ( 23 ), each data block including a plurality of data bits ( 20 ) for storing bit data; a first recognition bit ( 21 ) for storing a first recognition code; and a second recognition bit ( 22 ) for storing a second recognition code. The program memory stores program modules. The CPU updates and deletes data in data blocks, reads a first recognition code and a second recognition code in a data block in which bit data are to be read, and identifies whether the bit data are complete according to a combination of the first recognition code and the second recognition code. A related method for verifying data integrity is also disclosed.

Claims (32)

1. A system for verifying data integrity, the system comprising:

a non-volatile random access memory (NVRAM) comprising a plurality of data blocks, each data block comprising:

a plurality of data bits for storing bit data;

a first recognition bit for storing a first recognition code; and

a second recognition bit for storing a second recognition code; and

a central processing unit (CPU) for updating and deleting the bit data in the data blocks, reading a first recognition code and a second recognition code of any data block in which the bit data are to be read, and identifying incomplete bit data according to the first recognition code and the second recognition code.

2. The system as claimed in claim 1 , further comprising a program memory, the program memory comprising:

a memory cell obtaining module for obtaining enough memory cells from the NVRAM for storing bit data;

a data reading module for reading bit data from the data blocks;

a data writing module for writing bit data into the data blocks;

a data updating module for updating bit data in the first recognition bits, the second recognition bits, and the data bits of the data blocks; and

a data determining module for determining whether bit data in a data block are complete according to a combination of the first recognition bit and the second recognition bit of the data block.

3. The system as claimed in claim 1 , wherein the CPU identifies incomplete bit data by determining whether the first recognition code equals the second recognition code.

4. The system as claimed in claim 3 , wherein the CPU determines that the bit data are incomplete if the first recognition code equals the second recognition code.

5. The system as claimed in claim 3 , wherein the CPU determines that the bit data are complete if the first recognition code does not equal the second recognition code.

6. The system as claimed in claim 1 , wherein incomplete bit data means the bit data are invalid.

7. A method for verifying integrity of data stored in a memory of a system, comprising the steps of:

identifying a data block of said data stored in said memory;

identifying a first recognition code in front of said data block;

identifying a second recognition code behind said data block; and

verifying said first and second recognition codes to directly decide said integrity of said data block of said data.

8. The method as claimed in claim 7 , further comprising the step of updating said data block of said data with a new data block in said memory by means of the steps of:

replacing said first recognition code with said second recognition code;

replacing said data block with said new data block; and

substituting said second recognition code with a complement of said second recognition code.

9. The method as claimed in claim 7 , further comprising the step of deleting said data block of said data from said memory by means of the steps of:

retrieving said second recognition code; and

substituting said first recognition code with said second recognition code.

10. The method as claimed in claim 7 , further comprising the step of reading said data block of said data from said memory by means of the steps of:

retrieving said first and second recognition codes; and

retrieving said data block of said data as a readable status based on comparison of said first and second recognition codes.

11. The method as claimed in claim 7 , wherein said integrity of said data block is decided as being invalid when said first recognition code is identical to said second recognition code.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 7, 2018
From: HON HAI PRECISION INDUSTRY CO., LTD.
To: CLOUD NETWORK TECHNOLOGY SINGAPORE PTE. LTD.
Reel/Frame 045281/0269 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 24, 2004
From: WU, CHENG-MENG
To: HON HAI PRECISION INDUSTRY CO., LTD.
Reel/Frame 016032/0094 →