IP Library Granted Patent US 7,725,877
Granted Patent B2
US 7,725,877 · App. 10/997,504 · Granted May 25, 2010

Graphical program which includes an I/O node for hardware abstraction

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,725,877
App. No.
10/997,504
Granted
May 25, 2010
Kind
B2
Abstract

A system and method for creating a graphical program utilizing one or more input/output (I/O) nodes. An I/O node may be displayed in a first graphical program, where the I/O node may include associated generation code for programmatically generating execution-time code associated with the I/O node in the first graphical program. First input may be received to select a first I/O source or target corresponding to the first I/O node, e.g., from various supported hardware resources, and the associated generation code may be executed to programmatically generate or modify the execution-time code, e.g., at compilation or prior to execution of the first graphical program, to provide I/O to or from the first I/O source or target.

Claims (74)

1. A computer-implemented method for creating a first graphical program, the method comprising:

utilizing a computer to perform:

receiving first user input specifying a target device for the first graphical program, wherein the first graphical program comprises a plurality of interconnected nodes that visually indicate functionality of the first graphical program;

displaying a first I/O node in the first graphical program in response to second user input, wherein the first I/O node includes associated generation code for automatically generating execution-time code associated with the first I/O node;

receiving third user input specifying at least one I/O resource of the target device, wherein the third user input specifying at least one I/O resource of the target device assigns an alias to the first I/O node, wherein the alias indicates the specified I/O resource and further indicates an assigned one of a plurality of I/O configurations, each specifying a respective configuration of the specified I/O resource;

configuring the first I/O node to perform an I/O operation via the specified at least one I/O resource during execution of the first graphical program;

modifying an appearance of the first I/O node to reflect said configuring, wherein the modified appearance of the first I/O node indicates a type of the at least one I/O resource; and

the generation code associated with the first I/O node executing to automatically generate first execution-time code based on the specified at least one I/O resource and the indicated I/O configuration, wherein the automatically generated first execution-time code is associated with the first I/O node in the first graphical program, and wherein the automatically generated first execution-time code is executable to provide I/O to or from the at least one I/O resource.

2. The computer-implemented method of claim 1 , further comprising:

utilizing the computer to perform:

wherein the second user input specifies an I/O node type;

wherein the at least one I/O resource is in accordance with the specified I/O node type.

3. The computer-implemented method of claim 1 , further comprising:

utilizing the computer to perform:

executing the first graphical program, including executing the first I/O node, wherein said executing the first I/O node includes executing the first execution-time code.

4. The computer-implemented method of claim 1 , further comprising:

utilizing the computer to perform:

receiving further user input specifying a second at least one I/O resource; and

the generation code associated with the first I/O node automatically generating second execution-time code based on the further user input;

wherein the second execution-time code is associated with the first I/O node in the first graphical program in place of the first execution-time code; and

wherein the automatically generated second execution-time code is executable to provide I/O to or from the second at least one I/O resource.

5. The computer-implemented method of claim 1 ,

wherein the generation code is configured to automatically generate different types of execution-time code having different functionality for the first I/O node depending upon the target device and I/O resources specified.

6. The computer-implemented method of claim 1 ,

wherein the generation code executes to automatically generate the first execution-time code in response to input received to edit the first graphical program.

7. The computer-implemented method of claim 1 ,

wherein the generation code executes to automatically generate the first execution-time code when compiling the graphical program.

8. The computer-implemented method of claim 1 ,

wherein the first I/O node does not have any associated execution-time code when the first I/O node is displayed in the first graphical program; and

wherein said automatically generating the first execution-time code comprises creating execution-time code for the first I/O node.

9. The computer-implemented method of claim 1 ,

wherein the first I/O node has initial associated execution-time code when the first I/O node is displayed in the first graphical program; and

wherein said automatically generating the first execution-time code comprises replacing or modifying the initial execution-time code with the first execution-time code.

10. The computer-implemented method of claim 1 , the method further comprising:

utilizing the computer to perform:

receiving user input modifying one or more of:

the alias referenced by the I/O node;

which I/O configuration is assigned to the specified alias;

the I/O configuration assigned to the specified alias; or

which at least one I/O resource is indicated by the alias;

the generation code associated with the first I/O node executing to automatically generate second execution-time code based on the received user input, wherein the second execution-time code replaces the first execution-time code.

11. The computer-implemented method of claim 1 ,

wherein the at least one I/O resource corresponds to an entry in a hardware database, wherein the hardware database comprises a plurality of entries corresponding to I/O resources of a plurality of respective hardware devices.

12. The computer-implemented method of claim 11 ,

wherein at least one of the respective hardware devices is comprised on a processor, and is only accessible inside the processor.

13. The computer-implemented method of claim 11 ,

wherein at least one of the respective hardware devices is comprised on a programmable hardware element, and is only accessible inside the programmable hardware element.

14. The computer-implemented method of claim 1 ,

wherein the graphical program comprises a graphical data flow program.

15. The computer-implemented method of claim 1 , wherein the first I/O node further includes associated design-time behavior code configured to affect design-time behavior of the first I/O node, the method further comprising:

utilizing the computer to perform:

the design-time behavior code associated with the first I/O node executing to affect design-time behavior of the first I/O node in response to the first input.

16. The computer-implemented method of claim 15 ,

wherein the design-time behavior code is executable to:

affect the appearance of the node within the graphical program in response to receiving input to edit the graphical program; or

affect a user's experience of interacting with the first I/O node when editing the first graphical program.

17. The computer-implemented method of claim 1 , wherein the execution-time code comprises one or more of:

a software program stored in a memory and executable by a processor; and

a hardware configuration program useable for configuring a programmable hardware element.

18. A computer-accessible memory medium that stores program instructions executable by a processor to implement:

an I/O abstraction node for use in a graphical program comprising a plurality of interconnected nodes that visually indicate functionality of the graphical program, the I/O abstraction node comprising:

data specifying an iconic appearance, wherein the data are useable to display an iconic appearance representing the I/O abstraction node in response to including the I/O abstraction node in the graphical program;

one or more input and/or output terminals for connecting the I/O abstraction node to other nodes in the graphical program; and

associated generation code, wherein the generation code is configured to automatically generate execution-time I/O code associated with the I/O abstraction node in the graphical program in response to user input specifying at least one I/O resource of a target device, wherein the user input specifying at least one I/O resource of the target device assigns an alias to the first I/O node, and wherein the alias indicates the specified I/O resource and further indicates an assigned one of a plurality of I/O configurations, each specifying a respective configuration of the specified I/O resource;

wherein the execution-time I/O code is automatically generated based on the indicated specified I/O resource and the indicated I/O configuration, wherein the automatically generated execution-time I/O code is associated with the first I/O node in the graphical program, and wherein the automatically generated execution-time I/O code is executable to provide I/O to or from the at least one I/O resource;

wherein the data specifying the iconic appearance of the I/O abstraction node is modified in response to the user input specifying the at least one I/O resource of the target device, thereby modifying the iconic appearance of the I/O abstraction node to indicate the at least one I/O resource's type; and

wherein once the execution-time I/O code is generated, the first I/O node is configured to perform an I/O operation via the specified at least one I/O resource during execution of the first graphical program.

19. A computer-accessible memory medium that stores program instructions executable by a processor to:

receive first user input specifying a target device for the first graphical program, wherein the first graphical program comprises a plurality of interconnected nodes that visually indicate functionality of the first graphical program;

display a first I/O node in the first graphical program in response to second user input, wherein the first I/O node includes associated generation code for automatically generating execution-time code associated with the first I/O node;

receive third user input specifying at least one I/O resource of the target device, wherein the third user input specifying at least one I/O resource of the target device assigns an alias to the first I/O node, wherein the alias indicates the specified I/O resource and further indicates an assigned one of a plurality of I/O configurations, each specifying a respective configuration of the specified I/O resource;

configure the first I/O node to perform an I/O operation via the specified at least one I/O resource during execution of the first graphical program;

modify an appearance of the first I/O node to reflect said configuring, wherein the modified appearance of the first I/O node indicates a type of the at least one I/O resource; and

execute the generation code associated with the first I/O node to automatically generate first execution-time code based on the specified at least one I/O resource and the indicated I/O configuration, wherein the automatically generated first execution-time code is associated with the first I/O node in the first graphical program, and wherein the automatically generated first execution-time code is executable to provide I/O to or from the at least one I/O resource.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS (REEL/FRAME 057280/0028) Recorded Oct 13, 2023
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: NATIONAL INSTRUMENTS CORPORATION
Reel/Frame 065231/0466 →
RELEASE OF SECURITY INTEREST IN PATENTS (REEL/FRAME 052935/0001) Recorded Oct 13, 2023
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: NATIONAL INSTRUMENTS CORPORATION; PHASE MATRIX, INC.
Reel/Frame 065653/0463 →
SECURITY INTEREST Recorded Jun 18, 2021
From: NATIONAL INSTRUMENTS CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 057280/0028 →
SECURITY INTEREST Recorded Jun 14, 2020
From: NATIONAL INSTRUMENTS CORPORATION; PHASE MATRIX, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 052935/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 24, 2004
From: ANDRADE, HUGO A.; NOVACEK, MATTHEW E.; DAROWSKI, LUKASZ T.
To: NATIONAL INSTRUMENTS CORPORATION
Reel/Frame 016029/0053 →