Thread scheduling in chip multithreading processors
A computer system includes an integrated circuit that has a plurality of processing cores fabricated therein and configured to perform operations in parallel. Each processing core is configured to process multiple threads, where a thread is assigned to one of the plurality of processing cores dependent on a cache hit rate of the thread.
1. A method for thread scheduling on a chip multithreading processor (CMP), comprising:
identifying an L2 cache hit threshold for an L2 cache of the CMP;
estimating an aggregate L2 cache hit rate for a group of threads comprising a first plurality of threads and a second plurality of threads,
wherein the first plurality of threads have a first plurality of cache memory space requirements (CMSR) corresponding to cache localities of the first plurality of threads, and
wherein the second plurality of threads have a second plurality of CMSR corresponding to cache localities of the second plurality of threads;
comparing the aggregate L2 cache hit rate with the L2 cache hit threshold;
scheduling the group of threads in response to the L2 cache hit rate exceeding the L2 cache hit threshold, wherein scheduling the group comprises:
comparing the first plurality of CMSR with a pre-defined threshold;
assigning, in response to the first plurality of CMSR exceeding the pre-defined threshold, the first plurality of threads to a first processing core of the CMP;
comparing the second plurality of CMSR with the pre-defined threshold; and
assigning, in response to the second plurality of CMSR being less than the pre-defined threshold, the second plurality of threads to a second processing core of the CMP.
2. The method of claim 1 , wherein estimating the aggregate L2 cache hit rate comprises:
summing a first L2 cache hit rate of a first thread in the group and a second L2 cache hit rate of a second thread in the group.
3. The method of claim 1 , wherein estimating the aggregate L2 cache hit rate comprises:
averaging a first L2 cache hit rate of a first thread in the group and a second L2 cache hit rate of a second thread in the group.
4. The method of claim 1 , further comprising:
setting the L2 cache hit threshold for an L2 cache of the CMP.
5. The method of claim 1 , wherein the first processing core and the second processing core are located on a server.
6. The method of claim 1 , wherein the first thread is associated with a request from a first client.
7. The method of claim 1 , wherein the second thread is associated with a second client.
8. A system for thread scheduling, comprising:
a first processing core;
a second processing core;
an L2 memory comprising an L2 cache hit threshold;
a scheduler configured to:
estimate an aggregate L2 cache hit rate for a group of threads comprising a first plurality of threads and a second plurality of threads,
wherein the first plurality of threads have a first plurality of cache memory space requirements (CMSR) corresponding to cache localities of the first plurality of threads, and
wherein the second plurality of threads have a second plurality of CMSR corresponding to cache localities of the second plurality of threads;
compare the aggregate L2 cache hit rate with the L2 cache hit threshold;
schedule the group of threads on the first processing core and the second processing core in response to the L2 cache hit rate exceeding the L2 cache hit threshold, wherein scheduling the group of threads comprises:
comparing the first plurality of CMSR with a pre-defined threshold;
assigning, in response to the first plurality of CMSR exceeding the pre-defined threshold, the first plurality of threads to a first processing core of the CMP;
comparing the second plurality of CMSR with the pre-defined threshold; and
assigning, in response to the second plurality of CMSR being less than the pre-defined threshold, the second plurality of threads to a second processing core of the CMP.
9. The system of claim 8 , wherein the scheduler is on a server and the first thread is associated with a request from a first client.
10. The system of claim 8 , wherein the second thread is associated with a second client.