Semiconductor device and process of producing the same
View Patent ↗The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
1. A process of producing a semiconductor device, comprising the steps of:
forming a first polycrystalline silicon layer above a substrate; and
forming a second polycrystalline silicon layer,
wherein a lower surface of the second polycrystalline silicon layer is in contact with an upper surface of the first polycrystalline silicon layer, and the second polycrystalline silicon layer is thicker than the first polycrystalline silicon layer,
wherein the second polycrystalline silicon layer is in electrical connection with the first polycrystalline silicon layer and is adapted to be charged with substantially a same voltage as that of the first polycrystalline silicon layer,
wherein crystal grains of the first and second polycrystalline silicon layers have different grain sizes, and
wherein a temperature dependence of resistance of said first polycrystalline silicon layer is different from that of said second polycrystalline silicon layer.
2. The process of producing a semiconductor device according to claim 1 , wherein the first and second polycrystalline silicon layers are doped with an n-type impurity.
3. The process of producing a semiconductor device according to claim 1 , wherein the second polycrystalline silicon layer has a larger average grain size than that of the first polycrystalline silicon layer.
4. The process of producing a semiconductor device according to claim 1 , wherein the first and second polycrystalline silicon layers have impurities therein, and an impurity concentration of the second polycrystalline silicon layer is greater than that of the first polycrystalline silicon layer.
5. A process of producing a semiconductor device, comprising the steps of:
forming a first polycrystalline silicon layer above a substrate; and
forming a second polycrystalline silicon layer,
wherein a lower surface of the second polycrystalline silicon layer is in contact with an upper surface of the first polycrystalline silicon layer, and the second polycrystalline silicon layer is thicker than the first polycrystalline silicon layer,
wherein the second polycrystalline silicon layer is in electrical connection with the first polycrystalline silicon layer,
wherein the second polycrystalline silicon layer has a larger average grain size than that of the first polycrystalline silicon layer, and
wherein the second polycrystalline silicon layer has a larger concentration of a doped impurity than that of the first polycrystalline silicon layer.
6. The process of producing a semiconductor device according to claim 5 , wherein the first and second polycrystalline silicon layers are doped with an n-type impurity.