Multistandard video decoder
View Patent ↗Methods and systems for processing an encoded video stream are disclosed herein. Aspects of the method may comprise receiving on a chip, packetized data within the encoded video stream. An identifier within the received packetized data may be determined on the chip, where the identifier may define one of a plurality of encoding types associated with packets in the encoded video stream. A decoding process may be selected on the chip from a plurality of decoding processes, based on the determined identifier. A portion of the received packetized data in the encoded video stream may be decoded on the chip utilizing the selected decoding process. A header may be determined within the received packetized data that separates packets within the encoded video stream. A plurality of bytes within the received packetized data may be matched with a determined byte sequence.
1. A method for processing an encoded video stream, the method comprising:
receiving on a chip, packetized data within the encoded video stream;
determining on said chip, an identifier within said received packetized data that defines one of a plurality of encoding types associated with packets in the encoded video stream;
selecting on said chip, a decoding process from a plurality of decoding processes based on said determined identifier; and
decoding on said chip, at least a portion of said received packetized data in the encoded video stream utilizing said selected decoding process.
2. The method according to claim 1 , comprising determining on said chip, a start code within said received packetized data that separates packets within the encoded video stream.
3. The method according to claim 2 , comprising matching a plurality of bytes within said received packetized data with a determined byte sequence.
4. The method according to claim 3 , comprising removing said plurality of bytes from said received packetized data, if said plurality of bytes matches said determined byte sequence.
5. The method according to claim 1 , comprising decoding said at least a portion of said received packetized data utilizing one or more of a fixed length coding (FLC) process, a variable length coding (VLC) process and/or a context adaptive binary arithmetic coding (CABAC) process, if said determined identifier corresponds to H.264 video encoding.
6. The method according to claim 1 , comprising decoding said at least a portion of said received packetized data utilizing one or both of a FLC process and/or a VLC process, if said determined identifier corresponds to VC-1 video encoding.
7. The method according to claim 1 , comprising decoding said at least a portion of said received packetized data utilizing one or both of a FLC process and/or a VLC process, if said determined identifier corresponds to one or more of an H.261, H.263, H.263+, MPEG-1, MPEG-2 and/or MPEG-4 video encoding.
8. The method according to claim 1 , wherein said decoded packetized data comprises one or both of prediction pixels information and/or prediction error information.
9. The method according to claim 1 , comprising generating a decoded video stream utilizing at least a portion of said decoded packetized data.
10. The method according to claim 1 , comprising, for each of said plurality of decoding processes, decoding on said chip said at least a portion of said received packetized data utilizing one or more of inverse transformation, inverse quantization, and/or motion compensation.
11. A computer-readable storage having stored thereon, a computer program having at least one code section for processing an encoded video stream, the at least one code section being executable by a machine to perform steps comprising:
receiving on a chip, packetized data within the encoded video stream;
determining on said chip, an identifier within said received packetized data that defines one of a plurality of encoding types associated with packets in the encoded video stream;
selecting on said chip, a decoding process from a plurality of decoding processes based on said determined identifier; and
decoding on said chip, at least a portion of said received packetized data in the encoded video stream utilizing said selected decoding process.
12. The computer-readable storage according to claim 11 , comprising code for determining on said chip, a start code within said received packetized data that separates packets within the encoded video stream.
13. The computer-readable storage according to claim 12 , comprising code for matching a plurality of bytes within said received packetized data with a determined byte sequence.
14. The computer-readable storage according to claim 13 , comprising code for removing said plurality of bytes from said received packetized data, if said plurality of bytes matches said determined byte sequence.
15. The computer-readable storage according to claim 11 , comprising code for decoding said at least a portion of said received packetized data utilizing one or more of a fixed length coding (FLC) process, a variable length coding (VLC) process and/or a context adaptive binary arithmetic coding (CABAC) process, if said determined identifier corresponds to H.264 video encoding.
16. The computer-readable storage according to claim 11 , comprising code for decoding said at least a portion of said received packetized data utilizing one or both of a FLC process and/or a VLC process, if said determined identifier corresponds to VC-1 video encoding.
17. The computer-readable storage according to claim 11 , comprising code for decoding said at least a portion of said received packetized data utilizing one or both of a FLC process and/or a VLC process, if said determined identifier corresponds to one or more of H.261, H.263, H.263+, MPEG-1, MPEG-2 and/or MPEG-4 video encoding.
18. The computer-readable storage according to claim 11 , wherein said decoded packetized data comprises one or both of prediction pixels information and/or prediction error information.
19. The computer-readable storage according to claim 11 , comprising code for generating a decoded video stream utilizing at least a portion of said decoded packetized data.
20. The computer-readable storage according to claim 19 , comprising code for filtering said generated decoded video stream utilizing one or both of an overlapped transform process and/or a deblocking process.
21. A system for processing an encoded video stream, the system comprising:
at least a first processor operable to receive on a chip, packetized data within the encoded video stream;
said at least a first processor is operable to determine on said chip, an identifier within said received packetized data that defines one of a plurality of encoding types associated with packets in the encoded video stream;
at least a second processor operable to select on said chip, a decoding process from a plurality of decoding processes based on said determined identifier; and
said at least a second processor is operable to decode on said chip, at least a portion of said received packetized data in the encoded video stream utilizing said selected decoding process.
22. The system according to claim 21 , wherein said at least a first processor is operable to determine on said chip, a start code within said received packetized data that separates packets within the encoded video stream.
23. The system according to claim 22 , wherein said at least a first processor is operable to match a plurality of bytes within said received packetized data with a determined byte sequence.
24. The system according to claim 23 , wherein said at least a first processor is operable to remove said plurality of bytes from said received packetized data, if said plurality of bytes matches said determined byte sequence.
25. The system according to claim 21 , wherein said at least a second processor is operable to decode said at least a portion of said received packetized data utilizing one or more of a fixed length coding (FLC) process, a variable length coding (VLC) process and/or a context adaptive binary arithmetic coding (CABAC) process, if said determined identifier corresponds to H.264 video encoding.
26. The system according to claim 21 , wherein said at least a second processor is operable to decode said at least a portion of said received packetized data utilizing one or both of a FLC process and/or a VLC process, if said determined identifier corresponds to VC-1 video encoding.
27. The system according to claim 21 , wherein said at least a second processor is operable to decode said at least a portion of said received packetized data utilizing one or both of a FLC process and/or a VLC process, if said determined identifier corresponds to one or more of H.261, H.263, H.263+, MPEG-1, MPEG-2 and/or MPEG-4 video encoding.
28. The system according to claim 21 , wherein said decoded packetized data comprises one or both of prediction pixels information and/or prediction error information.
29. The system according to claim 21 , wherein said at least a second processor is operable to generate a decoded video stream utilizing at least a portion of said decoded packetized data.
30. The system according to claim 29 , wherein said at least a second processor is operable to filter said generated decoded video stream utilizing one or both of an overlapped transform process and/or a deblocking process.