Multilayered circuit board for high-speed, differential signals
The present invention provides a multilayered circuit board that can be used in high-density and high-speed electronic applications.
1 . A circuit board, comprising:
a first complaint pin via for receiving a first compliant pin of a connector, the first compliant pin via extending through a first dielectric layer of the circuit board;
a second complaint pin via for receiving a second compliant pin of the connector, the second compliant pin via extending through said first dielectric layer;
a first signal via electrically connected to a first transmission line disposed between a second and third dielectric layer of the circuit board, wherein the second dielectric layer is below the first dielectric layer and the third dielectric layer is below the second dielectric layer;
a second signal via electrically connected to a second transmission line disposed between the second and third dielectric layers;
a first link trace electrically connecting the first compliant pin via to the first signal via, the first link trace being disposed between the first and second dielectric layers; and
a second link trace electrically connecting the second compliant pin via to the second signal via, the second link trace being disposed between the first and second dielectric layers.
2 . The circuit board of claim 1 , wherein the first and second link traces are disposed on a top surface of the second dielectric layer.
3 . The circuit board of claim 1 , wherein the first and second transmission lines each comprise a strip of electrically conducting material.
4 . The circuit board of claim 3 , wherein the strips are disposed on the third dielectric layer.
5 . The circuit board of claim 1 , wherein a longitudinal axis of the first compliant pin via and a longitudinal axis of the second compliant pin via lie on a first plane, and a longitudinal axis of the first signal via and a longitudinal axis of the second signal via lie on a second plane, wherein the second plane is spaced apart from the first plane and is parallel with the first plane.
6 . The circuit board of claim 5 , the second plane is spaced apart from the first plane by a distance, wherein the distance is less than a length of the first link trace and less than a length of the second link trace.
7 . The circuit board of claim 6 , wherein the length of the first link trace is equal to the length of the second link trace.
8 . The circuit board of claim 1 , further comprising a conducting layer disposed on top of the first dielectric layer, wherein the first and second complaint pin vias extend through the conducting layer and are isolated therefrom by an anitpad.
9 . The circuit board of claim 1 , further comprising a conducting layer disposed between the second dielectric layer and the third dielectric layer.
10 . The circuit board of claim 9 , further comprising a fourth dielectric layer disposed between the conducting layer and the third dielectric layer.
11 . The circuit board of claim 1 , wherein the distance between the first and second compliant pin vias is less than the distance between the first and second signal vias.
12 . A circuit board, comprising:
a first complaint pin via for receiving a first compliant pin of a connector;
a second complaint pin via for receiving a second compliant pin of the connector;
a first signal via electrically connected to a first transmission line;
a second signal via electrically connected to a second transmission line;
a first link trace electrically connecting the first compliant pin via to the first signal via; and
a second link trace electrically connecting the second compliant pin via to the second signal via.
13 . The circuit board of claim 12 , wherein the first and second transmission lines each comprise a strip of electrically conducting material.
14 . The circuit board of claim 12 , wherein a longitudinal axis of the first compliant pin via and a longitudinal axis of the second compliant pin via lie on a first plane, and a longitudinal axis of the first signal via and a longitudinal axis of the second signal via lie on a second plane, wherein the second plane is spaced apart from the first plane and is parallel with the first plane.
15 . The circuit board of claim 14 , the second plane is spaced apart from the first plane by a distance, wherein the distance is less than a length of the first link trace and less than a length of the second link trace.
16 . The circuit board of claim 15 , wherein the length of the first link trace is equal to the length of the second link trace.
17 . The circuit board of claim 12 , further comprising a conducting layer disposed on top of a first dielectric layer, wherein the first and second complaint pin vias extend through the conducting layer and are isolated therefrom by an anitpad and extend through the first dielectric layer.
18 . The circuit board of claim 12 , wherein the distance between the first and second compliant pin vias is less than the distance between the first and second signal vias.
19 . The circuit board of claim 12 , wherein the signal vias and the compliant pin vias are independently tuned with antipads.