Sub-micron high input voltage tolerant input output (I/O) circuit which accommodates large power supply variations
View Patent ↗A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependant on the external voltages seen by the low voltage integrated circuit.
1. A system for protecting an integrated circuit from an over voltage, the system comprising:
a control voltage coupled to the integrated circuit;
a pad voltage from an external voltage source coupled to the integrated circuit at a pad node;
a bias voltage coupled to the integrated circuit at a bias node;
a first diode connected device;
a first switch disposed between the pad node and the bias node;
a second switch disposed between the pad node and a gate of the first switch; and
a third switch disposed between the bias node and the gate of the first switch,
wherein, if the control voltage has a value less than a predetermined value, the second switch is turned off and the third switch is turned on to thereby turn on the first switch to provide the bias voltage for the integrated circuit at the bias node, and
wherein the pad voltage is applied at the bias node as the bias voltage through the first diode connected device and the first switch.
2. The system of claim 1 , wherein the first diode connected device comprises a plurality of transistors.
3. The system of claim 2 , wherein the each of the plurality of transistor is diode connected.
4. The system of claim 2 , wherein the first switch is serially coupled with the plurality of transistors and wherein the plurality of transistors are serially coupled with each other.
5. The system of claim 1 , wherein each of the first, second, and third switches comprises a P-channel Metal Oxide Semiconductor (PMOS).
6. The system of claim 5 , wherein the first diode connected device comprises a plurality of diode connected P-channel Metal Oxide Semiconductors (PMOSs).
7. The system of claim 6 , further comprising a plurality of diode connected N-channel Metal Oxide Semiconductors (NMOSs) coupled between the bias node and a power supply voltage node.
8. The system of claim 1 , further comprising a second diode connected device, wherein the third switch is coupled to the gate of the first switch through the second diode connected device.
9. The system of claim 8 , wherein the first diode connected device comprises a plurality of first serially coupled transistors and the second diode connected device comprises a plurality of second serially coupled transistors.
10. The system of claim 1 , wherein, if the control voltage has a value greater than the predetermined value, the second switch is turned on and the third switch is turned off to thereby turn off the first switch.
11. The system of claim 1 , further comprising a second diode connected transistor coupled between the bias node and a power supply voltage node, wherein the second diode connected transistor and the power supply voltage node limit a maximum voltage level at the bias node.
12. A system for protecting an integrated circuit from an over voltage, the system comprising:
a control voltage coupled to the integrated circuit;
a pad voltage from an external voltage source coupled to the integrated circuit at a pad node;
a bias voltage coupled to the integrated circuit at a bias node;
a first diode connected device;
a first switch disposed between the pad node and the bias node;
a second switch disposed between the pad node and a gate of the first switch; and
a third switch disposed between the bias node and the gate of the first switch,
wherein, if the control voltage has a value less than a predetermined value, the second switch is turned off and the third switch is turned on to thereby turn on the first switch to provide the bias voltage for the integrated circuit at the bias node, and
wherein the third switch is coupled to the gate of the first switch through the first diode connected device.
13. The system of claim 12 , wherein if the control voltage has a value greater than the predetermined value the first switch is turned off, such that the pad voltage is not provided to the bias node through the first switch.
14. The system of claim 12 , wherein the first diode connected device comprises a plurality of transistors.
15. The system of claim 14 , wherein the each of the plurality of transistor is diode connected.
16. The system of claim 12 , further comprising a second diode connected device, wherein the pad voltage is applied at the bias node as the bias voltage through the second diode connected device and the first switch.
17. The system of claim 16 , wherein the first switch is serially coupled to the second diode connected device.
18. The system of claim 16 , wherein the second diode connected device comprises a plurality of serially coupled transistors.
19. The system of claim 12 , further comprising a second diode connected transistor coupled between the bias node and a power supply voltage node, wherein the second diode connected transistor and the power supply voltage node limit a maximum voltage level at the bias node.
20. A system for protecting an integrated circuit from an over voltage, the system comprising:
a control voltage coupled to the integrated circuit;
a pad voltage from an external voltage source coupled to the integrated circuit at a pad node;
a bias voltage coupled to the integrated circuit at a bias node;
a first diode connected device;
a first switch disposed between the pad node and the bias node;
a second switch disposed between the pad node and a gate of the first switch; and
a third switch disposed between the bias node and the gate of the first switch,
wherein, if the control voltage has a value less than a predetermined value, the second switch is turned off and the third switch is turned on to thereby turn on the first switch to provide the bias voltage for the integrated circuit at the bias node, and
wherein the second switch is turned off by applying the pad voltage to a gate of the second switch through the first diode connected device.
21. The system of claim 20 , further comprising a fourth switch disposed between the gate of the second switch and the pad terminal, wherein the pad voltage is applied to the gate of the second switch through the first diode connected device when the fourth switch is turned on.
22. The system of claim 20 , further comprising a second diode connected device, wherein the pad voltage is applied at the bias node as the bias voltage through the second diode connected device and the first switch.
23. The system of claim 20 , further comprising a second diode connected device, wherein the third switch is coupled to the gate of the first switch through the second diode connected device.
24. The system of claim 20 , further comprising a second diode connected transistor coupled between the bias node and a power supply voltage node, wherein the second diode connected transistor and the power supply voltage node limit a maximum voltage level at the bias node.
25. The system of claim 20 , further comprising a second diode connected device and a third diode connected device, wherein the third switch is coupled to the gate of the first switch through the second diode connected device and wherein the pad voltage is applied at the bias node as the bias voltage through the third diode connected device and the first switch.