Electronic device with electrostatic discharge protection

1 . An array substrate with electrostatic discharge (ESD) protection, comprising:

a substrate;

a plurality of conductive lines overlying the substrate along a first direction; and

a plurality of conductive segments overlying the substrate, wherein at least one of the plurality of conductive segments is disposed between every two conductive lines of the plurality of conductive lines, and wherein each conductive segment is electrically isolated from the conductive lines.

2 . The array substrate as claimed in claim 1 , wherein each of the plurality of conductive lines comprises a pair of conductive fins, wherein a first conductive fin of the pair of conductive fins extends towards a first side and a second conductive fin of the pair of conductive fins extends towards a second side.

3 . The array substrate as claimed in claim 2 , wherein the plurality of pairs of conductive fins and the plurality of conductive segment are arranged along a second direction distinct from the first direction.

4 . The array substrate as claimed in claim 3 , wherein the second direction is substantially perpendicular to the first direction.

5 . The array substrate as claimed in claim 3 , further comprising a plurality of common electrodes overlying the substrate, wherein each of the plurality of common electrodes is disposed between two conductive lines of the plurality of conductive lines, and wherein the common electrode is electrically isolated from the conductive segment.

6 . The array substrate as claimed in claim 5 , wherein each of the plurality of common electrodes comprises a pair of conductive fins, and wherein a first conductive fin of the pair of conductive fins extends towards a first side and a second conductive fin of the pair of conductive fins extends towards a second side.

7 . The array substrate as claimed in claim 6 , wherein the pair of conductive fins of each of the plurality of common electrodes, the pair of conductive fins of each of the plurality of conductive lines, and the conductive segment. are substantially arranged in a line.

8 . The array substrate as claimed in claim 1 , wherein the conductive lines are gate lines connecting to a gate electrode of a thin film transistor disposed on the substrate.

9 . A display device with electrostatic discharge (ESD) protection, comprising:

a display panel, comprising:

a substrate;

a plurality of conductive lines overlying the substrate along a first direction; and

a plurality of conductive segments overlying the substrate, wherein at least one of the plurality of conductive segments is disposed between every two conductive lines of the plurality of conductive lines, and wherein each conductive segment is electrically isolated from the conductive lines; and

a controller coupled to and driving the display panel to render an image in accordance with an input.

10 . The display device as claimed in claim 9 , wherein the display panel is a liquid crystal display (LCD). panel.

11 . The display device as claimed in claim 9 , wherein the display panel is an electroluminescent display panel comprising an electroluminescent layer.

12 . The display device as claimed in claim 11 , wherein the electroluminescent layer comprises a polymer material and the electroluminescent display panel is a polymer light emitting diode (PLED) display.

13 . The display device as claimed in claim 11 , wherein the electroluminescent layer comprises an organic material and the electroluminescent display panel is an organic light emitting diode (OLED) display.

14 . A method for fabricating an array substrate with electrostatic discharge (ESD) protection, comprising:

providing a substrate;

forming a plurality of gate lines connected by a conductive line over the substrate;

forming an interlayer dielectric layer overlying the plurality of gate lines and the conductive line;

forming a plurality of contact holes in the interlayer dielectric layer overlying the conductive layer, wherein the plurality of contact holes expose portions of the underlying conductive line between every two gate lines of the plurality of gate lines;

forming a conductive layer over the substrate and in the plurality of contact holes; and

defining the conductive layer and the conductive line underlying the plurality of contact holes to form a plurality of data lines overlying the plurality of gate lines and at least one conductive segment over the substrate between every two gate lines of the plurality of gate lines.

15 . The method as claimed in claim 14 , wherein during the step of forming the plurality of gate lines, a common electrode is formed over the substrate between every two gate lines of the plurality of gate lines, the common electrode electrically connected to the plurality of gate lines.

16 . The method as claimed in claim 14 , wherein during the step of forming the plurality of gate lines, a gate electrode of a thin film transistor is formed over the substrate, the gate electrode connected to the plurality of gate lines.

17 . The method as claimed in claim 14 , wherein during the step of forming the plurality of data lines, a source electrode and a drain electrode of the thin film transistor are formed over the interlayer dielectric layer, the source electrode electrically connected to the plurality of data lines.

18 . The method as claimed in claim 14 , wherein a definition of the conductive layer is performed by a photolithography procedure and a subsequent dry etching procedure.

19 . The method as claimed in claim 18 , wherein the dry etching comprises an over-etching procedure.

20 . The method as claimed in claim 18 , wherein the conductive layer overlying the first conductive line is entirely removed during the definition thereof.