Thin film transistor substrate and fabricating method thereof
View Patent ↗A thin film transistor substrate and a fabricating method thereof that are capable of improving an aperture ratio. A gate electrode on that substrate has an inclined head and a concave neck.
1. A method of fabricating a thin film transistor substrate, comprising:
forming a gate metal layer on a substrate; and
patterning the gate metal layer to form a gate line and a gate electrode extending from the gate line and having a head portion inclined at an angle greater than zero degrees with respect to the gate line and substantially parallel with a rubbing direction of the substrate.
2. The method as claimed in claim 1 , further comprising the steps of:
forming a gate insulating film on the substrate and over the gate electrode;
forming a semiconductor layer on the gate insulating film;
forming source and drain electrodes on the semiconductor layer so as to define a channel;
forming a protective layer on the gate insulating film and over the source and drain electrodes; and
forming a pixel electrode on the protective layer.
3. The method as claimed in claim 1 , further comprising the steps of:
forming a gate insulating film on the substrate in such a manner as to cover the gate electrode;
depositing first and second semiconductor layers and a metal layer on the gate insulating film;
patterning the metal layer and the second semiconductor layer to form source and drain electrodes;
providing a protective material layer on the first semiconductor layer in such a manner as to cover the source and drain electrodes, patterning the first semiconductor layer and the protective layer material to form a protective layer and a semiconductor pattern; and
forming a pixel electrode on the protective layer.
4. The method as claimed in claim 1 , further comprising the steps of:
forming a gate insulating film and a semiconductor material on the substrate in such as a manner to cover the gate electrode;
forming source and drain electrodes on the semiconductor material;
depositing a protective layer material on the gate insulating film in such a manner as to cover the source and drain electrodes, simultaneously patterning the semiconductor material and the protective layer material to form a semiconductor pattern and a protective layer; and
forming a pixel electrode on the protective layer.
5. The method as claimed in claim 1 , further comprising the steps of forming a gate electrode having a neck portion that is narrower than a maximum width of the head portion by less than about 5 μm.
6. The method as claimed in claim 5 , further comprising the steps of:
forming a gate insulating film over the gate electrode;
forming a semiconductor layer on the gate insulating film; and
forming source and drain electrodes on the semiconductor layer so as to define a channel.
7. The method as claimed in claim 6 , further comprising the steps of providing a protective material layer on the semiconductor layer.
8. The method as claimed in claim 7 , further comprising the steps of forming a pixel electrode on the protective layer.