Hardware security module (HSM) chip card
View Patent ↗Processing circuitry is integrated within a hardware security module (HSM) chip card. The processing circuitry is configured to operate in accordance with a set of program instructions stored in a memory integrated within the HSM chip card. The set of program instructions includes program instructions for implementing a public-key cryptography standard (PKCS). The PKCS includes processes for generating and storing a master key. The master key is to be stored in the memory integrated within the HSM chip card. Also, using the master key stored in the memory of the HSM chip card, the HSM chip card enables direct management control of standard chip cards.
1. A hardware security module (HSM) chip card, comprising:
processing circuitry integrated on the HSM chip card, the processing circuitry configured to operate in accordance with a set of program instructions; and
a memory integrated on the HSM chip card, the memory having the set of program instructions stored therein, wherein the set of program instructions includes program instructions for implementing a public-key cryptography standard (PKCS), the PKCS including processes for generating and storing a master key, wherein the master key is to be stored in the memory on the HSM chip card, the set of program instructions also including processes for enabling the HSM chip card to direct management control of standard chip cards using the master key stored in the memory of the HSM chip card.
2. A HSM chip card as recited in claim 1 , wherein the HSM chip card is a Java card compliant with Java Card Enterprise Software.
3. A HSM chip card as recited in claim 1 , wherein the set of program instructions for implementing the PKCS includes program instructions for exporting a Cryptographic Token Interface Standard known as PKCS#11.
4. A HSM chip card as recited in claim 1 , wherein the set of program instructions for implementing the PKCS includes program instructions for using the master key to perform encryption.
5. A HSM chip card as recited in claim 1 , wherein the set of program instructions for implementing the PKCS includes program instructions for extracting Rivest, Shamir, and Adleman (RSA) public key data.
6. A HSM chip card as recited in claim 1 , wherein the set of program instructions for implementing the PKCS includes program instructions for generating a unique Rivest, Shamir, and Adleman (RSA) key pair.
7. A HSM chip card as recited in claim 1 , wherein the set of program instructions for implementing the PKCS includes program instructions for using a Rivest, Shamir, and Adleman (RSA) key pair to unwrap a symmetric key to be used in wrapping and unwrapping the master key.
8. A HSM chip card as recited in claim 1 , wherein the set of program instructions for implementing the PKCS includes program instructions for wrapping and unwrapping the master key using a symmetric key.
9. A hardware security module (HSM) system, comprising:
a chip card including,
processing circuitry integrated on the chip card, the processing circuitry being configured to operate in accordance with a set of program instructions for implementing a public-key cryptography standard (PKCS), and
a memory integrated on the chip card, the memory having the set of program instructions for implementing the PKCS stored therein, wherein the set of program instructions for implementing the PKCS includes program instructions for generating a master key and storing the master key in the memory;
a chip card reader configured to interface with the chip card, the chip card reader enabling access to data and functionality within the chip card; and
a server defined to communicate with the chip card via the chip card reader.
10. A HSM system as recited in claim 9 , wherein the server includes a PKCS library to enable communication with the chip card.
11. A HSM system as recited in claim 9 , wherein the memory includes one or more applets and a virtual machine to execute the one or more applets, wherein the one or more applets are defined to implement the PKCS.
12. A HSM system as recited in claim 9 , wherein the chip card is a Java card compliant with Java Card Enterprise Software.
13. A HSM system as recited in claim 9 , wherein the set of program instructions for implementing the PKCS includes program instructions for exporting a Cryptographic Token Interface Standard known as PKCS#11.
14. A HSM system as recited in claim 9 , wherein the set of program instructions for implementing the PKCS includes program instructions for using a master key to perform encryption.
15. A method for providing a hardware security module (HSM), comprising:
providing a chip card having processing circuitry capable of operating in accordance with a set of instructions stored in a memory of the chip card;
loading a set of instructions for implementing a public-key cryptography standard (PKCS) into the memory of the chip card;
operating the chip card to generate a master key;
storing the master key in the memory of the chip card;
interfacing the chip card with a server configured to operate in accordance with the PKCS; and
networking the server to enable network entities external to the server and the chip card to interact with the chip card when properly authorized.
16. A method for providing a HSM as recited in claim 15 , further comprising:
requiring an entity to be properly authenticated in order to interact with the chip card via the server.
17. A method for providing a HSM as recited in claim 15 , wherein the PKCS is a Cryptographic Token Interface Standard known as PKCS#11.
18. A method for providing a HSM as recited in claim 15 , wherein the chip card is a Java card compliant with Java Card Enterprise Software, the Java card including an applet to enable the Java card to operate with a PKCS compliant device.