IP Library Patent Application 11005066
Patent Application
App. No. 11/005,066

Two processor architecture supporting decoupling of outer loop and inner loop in video decoder

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Quick Facts
Patent No.
US None
App. No.
11/005,066
Abstract

Presented herein are systems, methods, and apparatus for two processor architecture supporting decoupling of the outer loop and the inner loop in a video decoder. In one embodiment, there is presented a video decoder for decoding a data structure. The video decoder comprises an outer loop processor and an inner loop processor. The outer loop processor performs overhead processing for the data structure. The inner loop processor decodes the data structure.

Claims (34)

1 . A video decoder for decoding a data structure, said video decoder comprising:

an outer loop processor for performing overhead processing for the data structure; and

an inner loop processor for decoding the data structure.

2 . The video decoder of claim 1 , wherein the data structure comprises a slice.

3 . The video decoder of claim 1 , wherein performing the overhead processing comprises generating a reference list for the data structure.

4 . The video decoder of claim 3 , wherein the reference list comprises a list of reference pictures from which the data structure is predicted.

5 . The video decoder of claim 1 , further comprising:

a first queue for providing elements to the inner loop processor from the outer loop processor, the elements comprising a pointer indicating a location of the data structure.

6 . The video decoder of claim 5 , wherein the elements further comprise:

an indicator indicating a channel context.

7 . The video decoder of claim 5 , further comprising:

a second queue for providing elements from the inner loop processor to the outer loop processor.

8 . The video decoder of claim 1 , wherein the outer loop processer performs overhead processing for another data structure while the inner loop processor decodes the data structure.

9 . The video decoder of claim 1 , wherein the data structure comprises a slice, and further comprising:

a decoded picture buffer structure for storing picture indicators and outputting a particular one of the picture indicators when the outer loop processor performs overhead processing for each slice in a picture; and

an intermediate structure for storing the particular one of the picture indicators and outputting the particular one of the picture indicators when the inner loop processer decodes each slice in a picture indicated by the particular one of the picture indicators.

10 . A method for decoding a data structure, said method comprising:

performing overhead processing for the data structure at a first processor; and

decoding the data structure at a second processor.

11 . The method of claim 10 , wherein the data structure comprises a slice.

12 . The method of claim 10 , wherein performing the overhead processing comprises generating a reference list for the data structure.

13 . The method of claim 12 , wherein the reference list comprises a list of reference pictures from which the data structure is predicted.

14 . The method of claim 10 , further comprising:

providing elements to the second processor from the first processor, the elements comprising a pointer indicating a location of the data structure.

15 . The method of claim 14 , wherein the elements further comprise:

an indicator indicating a channel context.

16 . The method of claim 14 , further comprising:

providing elements from the second processor to the first processor.

17 . The method of claim 10 , wherein the first processor performs over head processing for another data structure while the second processor decodes the data structure.

18 . The method of claim 10 , wherein the data structure comprises a slice, and further comprising:

storing picture indicators in a decoded picture buffer structure;

outputting a particular one of the picture indicators from the decoded picture buffer structure when the outer loop processor performs overhead processing for each slice in a picture;

storing the particular one of the picture indicators in an intermediate structure; and

outputting the particular one of the picture indicators from the intermediate structure when the inner loop processer decodes each slice in a picture indicated by the particular one of the picture indicators.

Assignments (5)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2009
From: BROADCOM ADVANCED COMPRESSION GROUP, LLC
To: BROADCOM CORPORATION
Reel/Frame 022299/0916 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2005
From: KNIGHT, ROY
To: BROADCOM ADVANCED COMPRESSION GROUP, LLC
Reel/Frame 016337/0609 →