Method and system for efficient design verification of a motion adaptive deinterlacer
View Patent ↗In a video system, a method and system for efficient design verification of a motion adaptive deinterlacer (MAD) are provided. A MAD reference model may be configured via a configuration file to generate test parameters for the verification of a MAD hardware model. Test-bench interface drivers and a verification monitor may be utilized to transfer test parameters to the MAD hardware model and to verify simulated results. Modes of verification may comprise a normal mode, a pixel processing mode, and a field controller mode. During the normal mode, simulated pixel information and register settings generated by the pixel processor and field controller in the MAD hardware model may be compared to expected pixel information and register settings generated by the MAD reference model. During the pixel processing mode, expected and simulated pixel information may be compared. During the field controller mode, expected and simulated register settings may be compared.
1. A method for verifying a motion adaptive deinterlacer (MAD), the method comprising:
in a processor:
selecting a portion of a MAD hardware model for verification;
generating a plurality of test parameters by a MAD reference model to verify said selected portion of said MAD hardware model;
generating a plurality of simulation parameters in said selected portion of said MAD hardware model based on at least a portion of said generated plurality of test parameters; and
comparing said generated plurality of simulation parameters with at least a portion of said generated plurality of test parameters for verification of said motion adaptive deinterlacer.
2. The method according to claim 1 , further comprising selecting a verification mode for said MAD hardware model from a normal verification mode, a pixel processing verification mode, and a field controller verification mode.
3. The method according to claim 1 further comprising selecting a pixel processor and a field controller as said selected portion of said MAD hardware model when a normal verification mode is selected.
4. The method according to claim 1 , further comprising selecting a pixel processor as said selected portion of said MAD hardware model when a pixel processing verification mode is selected.
5. The method according to claim 1 , further comprising selecting a field controller as said selected portion of said MAD hardware model when a field controller verification mode is selected.
6. The method according to claim 1 , further comprising transferring said at least a portion of said generated plurality of test parameters generated by said MAD reference model to a plurality of test-bench interface drivers.
7. The method according to claim 6 , wherein said plurality of test-bench interface drivers comprise a pixel information interface driver and a register bus driver.
8. The method according to claim 7 , further comprising transferring a plurality of input pixel information to said pixel information interface driver.
9. The method according to claim 7 , further comprising transferring a plurality of input register settings and a plurality of expected register settings to said register bus driver.
10. The method according to claim 1 , further comprising transferring a plurality of expected pixel information to a verification monitor.
11. The method according to claim 1 , wherein said generated plurality of test parameters comprise a plurality of input pixel information, a plurality of expected pixel information, a plurality of input register settings, and a plurality of expected register settings when a normal verification mode is selected.
12. The method according to claim 1 , wherein said generated plurality of test parameters comprise a plurality of input pixel information and a plurality of expected pixel information when a pixel processing verification mode is selected.
13. The method according to claim 1 , wherein said generated plurality of test parameters comprise a plurality of input register settings and a plurality of expected register settings when a field controller verification mode is selected.
14. The method according to claim 1 , further comprising comparing a plurality of simulated pixel information and a plurality of simulated register settings generated by said selected portion of said MAD hardware model with a plurality of expected pixel information and a plurality of expected register settings when a normal verification mode is selected.
15. The method according to claim 1 , further comprising comparing a plurality of simulated pixel information generated by said selected portion of said MAD hardware model with a plurality of expected pixel information when a pixel processing verification mode is selected.
16. The method according to claim 1 , further comprising comparing a plurality of simulated register settings generated by said selected portion of said MAD hardware model with a plurality of expected register settings when a field controller verification mode is selected.
17. A computer-readable medium having stored thereon, a computer program having at least one code section for verifying a motion adaptive deinterlacer (MAD), the at least one code section being executable by a machine for causing the machine to perform steps comprising:
selecting a portion of a MAD hardware model for verification;
generating a plurality of test parameters by a MAD reference model to verify said selected portion of said MAD hardware model;
generating a plurality of simulation parameters in said selected portion of said MAD hardware model based on at least a portion of said generated plurality of test parameters; and
comparing said generated plurality of simulation parameters with at least a portion of said generated plurality of test parameters for verification of said motion adaptive deinterlacer.
18. The computer-readable medium according to claim 17 , wherein said at least one code section comprises code for selecting a verification mode for said MAD hardware model from a normal verification mode, a pixel processing verification mode, and a field controller verification mode.
19. The computer-readable medium according to claim 17 , wherein said at least one code section comprises code for selecting a pixel processor and a field controller as said selected portion of said MAD hardware model when a normal verification mode is selected.
20. The computer-readable medium according to claim 17 , wherein said at least one code section comprises code for selecting a pixel processor as said selected portion of said MAD hardware model when a pixel processing verification mode is selected.
21. The computer-readable medium according to claim 17 , wherein said at least one code section comprises code for selecting a field controller as said selected portion of said MAD hardware model when a field controller verification mode is selected.
22. The computer-readable medium according to claim 17 , wherein said at least one code section comprises code for transferring said at least a portion of said generated plurality of test parameters generated by said MAD reference model to a plurality of test-bench inter-face drivers.
23. The computer-readable medium according to claim 22 , wherein said plurality of test-bench interface drivers comprise a pixel information interface driver and a register bus driver.
24. The computer-readable medium according to claim 23 , wherein said at least one code section comprises code for transferring a plurality of input pixel information to said pixel information interface driver.
25. The computer-readable medium according to claim 23 , wherein said at least one code section comprises code for transferring a plurality of input register settings and a plurality of expected register settings to said register bus driver.
26. The computer-readable medium according to claim 17 , wherein said at least one code section comprises code for transferring a plurality of expected pixel information to a verification monitor.
27. The computer-readable medium according to claim 17 , wherein said generated plurality of test parameters comprise a plurality of input pixel information, a plurality of expected pixel information, a plurality of input register settings, and a plurality of expected register settings when a normal verification mode is selected.
28. The computer-readable medium according to claim 17 , wherein said generated plurality of test parameters comprise a plurality of input pixel information and a plurality of expected pixel information when a pixel processing verification mode is selected.
29. The computer-readable medium according to claim 17 , wherein said generated plurality of test parameters comprise a plurality of input register settings and a plurality of expected register settings when a field controller verification mode is selected.
30. The computer-readable medium according to claim 17 , wherein said at least one code section comprises code for comparing a plurality of simulated pixel information and a plurality of simulated register settings generated by said selected portion of said MAD hardware model with a plurality of expected pixel information and a plurality of expected register settings when a normal verification mode is selected.
31. The computer-readable medium according to claim 17 , wherein said at least one code section comprises code for comparing a plurality of simulated pixel information generated by said selected portion of said MAD hardware model with a plurality of expected pixel information when a pixel processing verification mode is selected.
32. The computer-readable medium according to claim 17 , wherein said at least one code section comprises code for comparing a plurality of simulated register settings generated by said selected portion of said MAD hardware model with a plurality of expected register settings when a field controller verification mode is selected.
33. A system for verifying a motion adaptive deinterlacer (MAD), the system comprising:
at least one processor that selects a portion of a MAD hardware model for verification;
said at least one processor generates a plurality of test parameters to verify said selected portion of said MAD hardware model;
said selected portion of said MAD hardware model generates a plurality of simulation parameters based on at least a portion of said generated plurality of test parameters; and
said at least one processor compares said generated plurality of simulation parameters with at least a portion of said generated plurality of test parameters for verification of said motion adaptive deinterlacer.
34. The system according to claim 33 , wherein at least one memory stores a configuration file for generating said plurality of test parameters.
35. The system according to claim 33 , wherein said at least one processor selects a verification mode for said MAD hardware model from a normal verification mode, a pixel processing verification mode, and a field controller verification mode.
36. The system according to claim 33 , wherein said at least one processor selects a pixel processor and a field controller as said selected portion of said MAD hardware model when a normal verification mode is selected.
37. The system according to claim 33 , wherein said at least one processor selects a pixel processor as said selected portion of said MAD hardware model when a pixel processing verification mode is selected.
38. The system according to claim 33 , wherein said at least one processor selects a field controller as said selected portion of said MAD hardware model when a field controller verification mode is selected.
39. The system according to claim 33 , wherein said at least one processor compares a plurality of simulated pixel information and a plurality of simulated register settings generated by said selected portion of said MAD hardware model with a plurality of expected pixel information and a plurality of expected register settings when a normal verification mode is selected.
40. The system according to claim 33 , wherein said at least one processor compares a plurality of simulated pixel information generated by said selected portion of said MAD hardware model with a plurality of expected pixel information when a pixel processing verification mode is selected.
41. The system according to claim 33 , wherein said at least one processor compares a plurality of simulated register settings generated by said selected portion of said MAD hardware model with a plurality of expected register settings when a field controller verification mode is selected.
42. A method for verifying a motion adaptive deinterlacer (MAD), the method comprising:
in a processor, selecting either one of a pixel processor and a field controller for separate verification, wherein said motion adaptive deinterlacer comprises said pixel processor and said field controller; and
in said processor, simulating said selected one of said pixel processor and said field controller to verify design and/or operation of said selected one of said pixel processor and said field controller.
43. The method according to claim 42 , further comprising selecting said pixel processor when a pixel processing verification mode is selected.
44. The method according to claim 43 , further comprising generating a plurality of input pixel information and a plurality of expected pixel information when said pixel processing verification mode is selected.
45. The method according to claim 44 , further comprising comparing a plurality of simulated pixel information with said plurality of expected pixel information when said pixel processing verification mode is selected.
46. The method according to claim 42 , further comprising selecting said field controller when a field controller verification mode is selected.
47. The method according to claim 46 , further comprising generating a plurality of input register settings and a plurality of expected register settings when said field controller verification mode is selected.
48. The method according to claim 47 , further comprising comparing a plurality of simulated register settings with said plurality of expected register settings when said field controller verification mode is selected.