IP Library Granted Patent US 7,216,422
Granted Patent B2
US 7,216,422 · App. 11/007,010 · Granted May 15, 2007

Method of forming a capacitor assembly in a circuit board

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Quick Facts
Patent No.
US 7,216,422
App. No.
11/007,010
Granted
May 15, 2007
Kind
B2
Abstract

A circuit board includes an assembly having first and second power reference plane layers, and an insulator layer between the first and second power reference plane layers. Discrete decoupling capacitors are further provided with the assembly. Additional layers are provided above and below the assembly.

Claims (10)

1. A method of forming an assembly for use in a circuit board, comprising:

providing a dielectric layer;

forming plural openings in the dielectric layer;

placing discrete capacitors in the plural openings;

forming a roughened profile on each electrode of each capacitor;

abutting a first and a second power reference layers to the respective surfaces of the dielectric layer;

electrically connecting the first and the second power reference layers to the respective electrodes of the capacitors by contacting the roughened profile of each electrode to the respective power reference layers; and

compressing the first and the second power reference layers to the respective surfaces of the dielectric layer to maintain electrical contact between the first and the second power reference layers and the capacitors.

2. The method of claim 1 , wherein forming the roughened profile comprises performing one of scoring, etching, and dendritic plating.

3. The method of claim 1 , wherein forming the roughened profile comprises forming bumps on a surface of each electrode.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 21, 2007
From: NCR CORPORATION
To: TERADATA US, INC.
Reel/Frame 020540/0786 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2004
From: FAN, JUN; KNIGHTEN, JAMES L.; ALEXANDER, ARTHUR R.; SMITH, NORMAN W.
To: NCR CORPORATION
Reel/Frame 016073/0718 →