IP Library Granted Patent US 7,091,549
Granted Patent B2
US 7,091,549 · App. 11/007,885 · Granted Aug 15, 2006

Programmable memory devices supported by semiconductor substrates

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Quick Facts
Patent No.
US 7,091,549
App. No.
11/007,885
Granted
Aug 15, 2006
Kind
B2
Abstract

The invention includes a memory device supported by a semiconductor substrate and comprising in ascending order from the substrate: a floating gate, a dielectric material, a layer consisting essentially of tungsten nitride, a first mass consisting essentially of tungsten, and a second mass consisting essentially of one or more nitride compounds. The invention includes a memory device having a floating gate and a dielectric material over the floating gate. The device has a mass consisting essentially of tungsten over the dielectric material, with the mass having a pair of opposing sidewalls. A pair of sidewall spacers are along the opposing sidewalls of the mass. The sidewall spacers comprise a first layer consisting essentially of one or more nitride compounds and a second layer different from the first layer. The invention includes methods of making memory devices.

Claims (33)

1. A programmable memory device supported by a semiconductor substrate and comprising:

a floating gate over the substrate;

a dielectric material over the floating gate;

a mass consisting essentially of W over the dielectric material, the mass comprising a pair of opposing sidewalls; and

a pair of sidewall spacers along the opposing sidewalls of the mass, the sidewall spacers comprising a first layer consisting essentially of WN x and a second layer different from the first layer, wherein the second layer of the sidewall spacers consists essentially of silicon.

2. The device of claim 1 wherein the programmable memory device is a flash device.

3. The device of claim 1 wherein the dielectric material comprises one or both of silicon nitride and silicon dioxide.

4. The device of claim 1 wherein the mass consists essentially of WN x .

5. The device of claim 1 wherein the first layer of the sidewall spacers is physically against the mass.

6. The device of claim 1 wherein the second layer of the sidewall spacers consists essentially of silicon dioxide.

7. A programmable memory device supported by a semiconductor substrate and comprising:

a floating gate over the substrate;

a dielectric material over the floating gate;

a mass consisting essentially of W over the dielectric material, the mass comprising a pair of opposing sidewalls; and

a pair of sidewall spacers along and physically against the opposing sidewalls of the mass, the sidewall spacers comprising a first layer consisting essentially of WN x and a second layer different from the first layer, wherein:

the second layer of the sidewall spacers is laterally outward of the first layer, and comprises silicon dioxide; and

the sidewall spacers comprise a third layer laterally outward of the second layer, and comprises silicon nitride.

8. The device of claim 7 wherein the programmable memory device is a flash device.

9. The device of claim 7 wherein the dielectric material comprises one or both of silicon nitride and silicon dioxide.

10. The device of claim 7 wherein the mass consists essentially of WN x .

11. The device of claim 7 wherein the second layer of the sidewall spacers consists essentially of silicon dioxide.

12. A programmable memory device supported by a semiconductor substrate and comprising:

a floating gate over the substrate;

a dielectric material over the floating gate;

a first layer consisting essentially of WN x over the dielectric material;

a mass consisting essentially of W over the first layer;

a second layer consisting essentially of one or more nitride compounds over the mass; the mass, first layer and second layer being comprised by a stack having a pair of opposing sidewalls; and

a pair of sidewall spacers along and physically against the opposing sidewalls of the stack, the sidewall spacers comprising a first portion and a second portion different from the first portion, wherein the first portion consists essentially of WN x and the second portion consists essentially of silicon.

13. The device of claim 12 wherein the programmable memory device is a flash device.

14. The device of claim 12 wherein the dielectric material comprises one or both of silicon nitride and silicon dioxide.

15. The device of claim 12 wherein the mass consists essentially of WN x .

16. The device of claim 12 wherein the first portion of the sidewall spacers is physically against the mass.

17. The device of claim 12 wherein the second portion of the sidewall spacers consists essentially of silicon dioxide.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →