Semiconductor device with a nonvolatile semiconductor memory circuit and a plurality of IO blocks
View Patent ↗Only by replacing a conventional fuse element used for a redundant repair of a memory with a CMOS device, since physical processing is not required, there is an advantage on a circuit area in which the upper interconnection can be utilized. However, on a design of a semiconductor device, since the CMOS device requires application of a high voltage for rewriting, there is a problem of being subjected constraint of an arrangement of an interconnection or a semiconductor circuit. For that reason, by arranging the nonvolatile semiconductor memory circuit provided with the nonvolatile memory device which is constituted of a CMOS device between the IO blocks arranged at the periphery of the chip, physical processing due to replacing the conventional fuse element with the CMOS device will not be needed, so that while keeping an advantage on a circuit area that the upper interconnection can be utilized, the problem of the arrangement in consideration of high voltage application can be resolved.
1. A semiconductor device, comprising:
a semiconductor memory circuit arranged in a central area of a chip;
a plurality of IO blocks which are arranged in a periphery of the chip, each inputting and outputting a signal, a supply potential or a ground potential; and
a nonvolatile semiconductor memory circuit which is arranged in the periphery of the chip used for a redundant repair function of said semiconductor memory circuit,
wherein said nonvolatile semiconductor memory circuit comprises
a nonvolatile memory device constituted of an electrically readable and writable CMOS device,
a control circuit for producing a control signal which controls writing to said nonvolatile memory device according to an address signal,
an address signal line for supplying said address signal to said control circuit,
an input data line for supplying data written to said nonvolatile memory device synchronizing with said control signal,
an output data line for outputting data having been written to said nonvolatile memory device to said semiconductor memory circuit, wherein;
said plurality of IO blocks is arranged in a ring shape along the periphery of the chip, and
said nonvolatile semiconductor memory circuit is arranged between adjacent IO blocks of said plurality of IO blocks.
2. The semiconductor device according to claim 1 , wherein said IO block comprises a plurality of transistors which have different gate oxide thicknesses, respectively.
3. The semiconductor device according to claim 2 , wherein a transistor which constitutes said nonvolatile memory device is formed by employing the same process as that of forming a first transistor which has a first gate oxide thickness among a plurality of transistors constituting said IO block.
4. The semiconductor device according to claim 2 , wherein a transistor which constitutes said control circuit is formed in the same process as that of forming a second transistor which has a second gate oxide thickness among a plurality of transistors constituting said IO block.
5. The semiconductor device according to claim 1 , wherein first and second power supply lines for supplying the supply potential to said IO block, and a third power supply line for supplying the ground potential to said IO block are interconnected in a ring shape so as to pass through over said plurality of IO blocks.
6. The semiconductor device according to claim 5 , wherein a power supply line for supplying the supply potential to said nonvolatile semiconductor memory circuit is also used as said first and second power supply lines in a ring shape, and a power supply line for supplying the ground potential to said nonvolatile semiconductor memory circuit is also used as said third power supply line in a ring shape.
7. The semiconductor device according to claim 5 , wherein said address signal line and said input data line in said nonvolatile semiconductor memory circuit are interconnected in a ring shape in parallel with said first and second, and third power supply lines.
8. The semiconductor device according to claim 3 , wherein a transistor which constitutes said IO block and has a respective gate oxide thickness, and said transistor which constitutes said nonvolatile memory device of said nonvolatile semiconductor memory circuit are arranged in a ring shape.
9. The semiconductor device according to claim 4 , wherein a transistor which constitutes said IO block and has a respective gate oxide thickness, and said transistor which constitutes said control circuit of said nonvolatile semiconductor memory circuit are arranged in a ring shape.
10. The semiconductor device according to claim 1 , wherein data written to the nonvolatile memory device of said nonvolatile semiconductor memory circuit are used for fixing a gate of said semiconductor memory circuit.
11. The semiconductor device according to claim 1 , wherein said nonvolatile semiconductor memory circuit is arranged so as to be a located where a line length of the output data line which supplies data having been written to said nonvolatile memory device to said semiconductor memory circuit may become minimum with respect to a physical arrangement location of said semiconductor memory circuit.