Device for preventing erroneous synchronization in wireless communication apparatus
View Patent ↗An erroneous synchronization preventing device includes a pattern detector detecting a sync pattern from received data with a broader sync window to output a sync detection notice and a sync timing. On receipt of the notice, a packet header detector checks an error in a header field of the received data, and, if detecting no error, outputs a header-normally-received notice, on receipt of which the timing corrector makes the inner timing synchronous with the sync timing to output a timing correction end notice. The mode manager in turn outputs a change notice. The pattern detector then detects the sync pattern with a narrower sync window. Unless the end notice is received within a predetermined period as from receipt of the change notice, a detection period monitor outputs an out-of-synchronism notice. The mode manager then outputs a restoration command for instructing detection of the sync pattern with the broader sync window. Disconnection of a communication link due to erroneous synchronization will be avoided.
1. A device for preventing erroneous synchronization in a wireless communication apparatus operable in a power saving mode and in a normal mode for transmitting or receiving information in a form of packet, said device including:
a mode manager for outputting a restoration command for instructing detection of a sync pattern with a broader sync window and a change notice for notifying change to the normal mode;
a pattern detector for using the broader sync window and a narrower sync window than the broader sync window when said mode manager outputs the restoration command and the change notice, respectively, to detect the sync pattern contained in a sync field of the received information;
a timing corrector for synchronizing inner timing in the apparatus with the sync pattern detected by said pattern detector; and
a detection period monitor for outputting an out-of-sync notice to said mode manager when said pattern detector does not detect the sync pattern within a predetermined period as from a time said mode manager outputs the change notice;
said mode manager outputting the restoration command to said pattern detector at a time of reversion from the power saving mode to the normal mode and on receipt of the out-of-sync notice from said detection period monitor;
said mode manager outputting the change notice to said pattern detector and to said detection period monitor when said timing corrector completes a processing of synchronization of the inner timing.
2. The device according to claim 1 , further comprising:
a packet header detector for using an error code contained in a header field, when said pattern detector detects the sync pattern, to detect an error in the header field of the received information;
said timing corrector synchronizing an inner timing when said packet header detector detects a header field free from an error;
said detection period monitor outputting the out-of-sync notice to said mode manager when said packet header detector does not detect a header field free from an error within a predetermined time as from a time of outputting the change notice by said mode manager.
3. A device for preventing erroneous synchronization in a wireless communication apparatus operable in a power saving mode and in a normal mode for transmitting or receiving information in a form of packet, said device including:
a mode manager for outputting a restoration command for instructing detection of a sync pattern with a broader sync window and a change notice for notifying change to the normal mode;
a pattern detector for using the broader sync window and a narrow sync window than the broader sync window when said mode manager outputs the restoration command and the change notice, respectively, to detect the sync pattern contained in a sync field of the received information;
a normal receipt counter for monitoring successive detections of the sync pattern by said pattern detector; and
a timing corrector for synchronizing inner timing in the apparatus with the sync pattern detected by said pattern detector when a count of detections monitored by said normal receipt counter exceeds a predetermined value;
said mode manager outputting the restoration command to said pattern detector at a time of reversion from the power saving mode to the normal mode;
said mode manager outputting the change notice to said pattern detector when said timing corrector completes a processing of synchronization of the inner timing.
4. The device according to claim 3 , further comprising:
a packet header detector for using an error code contained in a header field, when said pattern detector detects the sync pattern, to detect an error in the header field of the received information;
said normal receipt counter monitoring successive detections of a header field free from an error by said packet header detector.