IP Library Granted Patent US 7,064,060
Granted Patent B2
US 7,064,060 · App. 11/010,344 · Granted Jun 20, 2006

Method for manufacturing semiconductor device

Assignee: Sanyo Electric Co., Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,064,060
App. No.
11/010,344
Granted
Jun 20, 2006
Kind
B2
Abstract

A heat treatment is performed to an insulating film composition, formed on a semiconductor substrate, at a temperature of 350° C. in an inert gas ambient to form a non-porous insulating film. Next, dry etching is performed using a resist pattern as a mask to form a trench in the non-porous insulating film, ashing is performed to remove the resist pattern, and the surface of the semiconductor substrate is cleaned. Thereafter, a second heat treatment is performed for the non-porous insulating film to form a porous insulating film. Since the second heat treatment is performed in an oxidizing-gas atmosphere, the pore-generating material can be removed at a temperature lower than the temperature of conventional methods to form an insulating film having a low dielectric constant.

Claims (19)

1. A method of manufacturing a semiconductor device comprising:

applying an insulating film composition containing an insulating film precursor and a pore-generating material onto a semiconductor substrate;

first heat treating said insulating film composition at a first temperature, not exceeding 350° C., in an inert-gas ambient to polymerize said insulating film precursor and form a non-porous film;

forming a chemical mechanical polishing (CMP) stopper film on said non-porous insulating film;

forming a resist pattern on said CMP stopper film;

dry etching said CMP stopper film and said non-porous insulating film using said resist pattern as a mask to form a trench in said non-porous insulating film;

removing said resist pattern by ashing;

cleaning said semiconductor substrate after the ashing;

after the cleaning, second heat treating said non-porous insulating film at a second temperature that is no higher than the first temperature in an oxidizing-gas ambient, removing said pore-generating material from said non-porous insulating film, thereby forming a porous insulating film;

forming a barrier metal film on said CMP stopper film and on inner surfaces of said trench;

forming a copper layer on said barrier metal film, filling said trench; and

polishing said copper layer and said barrier metal film by CMP, thereby forming a copper wiring.

2. The method of manufacturing a semiconductor device according to claim 1 , wherein if the first temperature is T 1 and duration of the first heat treating is t 1 , and the second temperature is T 2 and duration of the second heat treating is t 2 , then:

300° C.≦T 1 ≦400° C.,

250° C.≦T 2 ≦350° C.,

and

t 1 =t 2 .

3. The method manufacturing a semiconductor device according to claim 1 , including performing the ashing in a reducing ambient containing hydrogen.

4. The method manufacturing a semiconductor device according to claim 1 , wherein said porous insulating film is selected from the group consisting of a methyl silsesquioxane film, an hydrogenated silsesquioxane film, an organic-inorganic hybrid film, a polyimide derivative film, a polyarylether derivative film, a polyquinone derivative film, and a polyparaxylene derivative film.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 20, 2005
From: SEMICONDUCTOR LEADING EDGE TECHNOLOGIES, INC.
To: SANYO ELECTRIC CO., LTD.
Reel/Frame 016041/0608 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2004
From: MISAWA, KAORI; OHASHI, NAOFUMI
To: SEMICONDUCTOR LEADING EDGE TECHNOLOGIES, INC.
Reel/Frame 016080/0829 →
Priority Claims (1)
JP 2004-051432 · Feb 26, 2004 · national
Continuity (1)
Related Publication 20050191847A1 · Sep 1, 2005