Method for fabricating thin film transistor with multiple gates using metal induced lateral crystallization
View Patent ↗A thin film transistor with multiple gates using an MILC process which is capable of materializing multiple gates without increasing dimensions and a method thereof. The thin film transistor has a semiconductor layer which is formed on a insulating substrate in a zigzag shape; and a gate electrode which is equipped with one or more slots intersecting with the semiconductor layer, the semiconductor layer includes two or more body parts intersecting with the gate electrode; and one or more connection parts connecting each neighboring body part, wherein a part overlapping the semiconductor layer in the gate electrode acts as a multiple gate, and MILC surfaces are formed at a part which does not intersect with the gate electrode in the semiconductor layer.
1. A method of fabricating a thin film transistor with multiple gates using the MILC process comprising:
forming a multi-semiconductor layer comprising neighboring polycrystalline silicon films using the MILC process on an insulating substrate;
forming a gate electrode intersecting with the multi-semiconductor layer;
forming contact holes so that portions of the multi-semiconductor layer are exposed;
forming source/drain electrodes each contacting one of the exposed portions of the multi-semiconductor layer; and
forming a link contacting other ones of the exposed portions of the multi-semiconductor layer to connect at least two semiconductor layers of the multi-semiconductor layer to each other.
2. The method of claim 1 , wherein the gate electrode is equipped with one or more slots intersecting with the multi-semiconductor layer.
3. The method of claim 2 , wherein the multi-semiconductor layer has MILC surfaces at parts corresponding to the slots of the gate electrode.
4. The method of claim 1 , wherein the link is made of the same material as the source/drain electrodes.
5. The method of claim 1 , wherein the forming of the source/drain electrodes and the forming of the link are simultaneously done.
6. The method of claim 1 , further comprising:
forming a buffer layer;
forming an amorphous silicon layer on the buffer layer;
forming a blocking layer on the amorphous silicon layer;
forming a photosensitive film on the blocking layer;
patterning the blocking layer using the photosensitive film as a mask;
reflowing the photosensitive film so as to completely cover the patterned blocking layer;
depositing a metal layer;
removing the photosensitive film; and
crystallizing the amorphous silicon layer using the MILC process.
7. The method of claim 6 , wherein an MILC surface produced when the MILC process proceeds does not exist in channel regions of the multi-semiconductor layer.
8. The method of claim 6 , wherein the metal layer is capable of forming a metal silicide and is deposited on a front surface of the silicon layer at a thickness in a range of several angstroms to hundreds of angstroms.
9. A method of fabricating a thin film transistor with multiple gates using the MILC process comprising:
forming a multi-semiconductor layer comprising neighboring polycrystalline silicon films using the MILC process on an insulating substrate;
forming a gate electrode intersecting with the multi-semiconductor layer;
forming contact holes so that portions of the multi-semiconductor layer are exposed; and
forming a link contacting the exposed portions of the multi-semiconductor layer to connect at least two semiconductor layers of the multi-semiconductor layer to each other.
10. The method of claim 9 , wherein the link is made of the same material as the gate electrode.
11. The method of claim 9 , wherein the forming of the gate electrode and the forming of the link are simultaneously done.
12. The method of claim 9 , wherein the gate electrode is equipped with one or more slots intersecting with the multi-semiconductor layer.
13. The method of 12 , wherein the multi-semiconductor layer has MILC surfaces at parts corresponding to the slots of the gate electrode.
14. The method of claim 9 , further comprising:
forming a buffer layer;
forming an amorphous silicon layer on the buffer layer;
forming a blocking layer on the amorphous silicon layer;
forming a photosensitive film on the blocking layer;
patterning the blocking layer using the photosensitive film as a mask;
reflowing the photosensitive film so as to completely cover the patterned blocking layer;
depositing a metal layer;
removing the photosensitive film; and
crystallizing the amorphous silicon layer using the MILC process.
15. The method of claim 14 , wherein an MILC surface produced when the MILC process proceeds does not exist in channel regions of the multi-semiconductor layer.
16. The method of claim 14 , wherein the metal layer is capable of forming a metal silicide and is deposited on a front surface of the silicon layer at a thickness in a range of several angstroms to hundreds of angstroms.
17. The method of claim 1 , wherein the forming of the gate electrode intersecting with the multi-semiconductor layer forms the multiple gates of the thin film transistor.
18. The method of claim 1 , wherein the forming of the gate electrode intersecting with the multi-semiconductor layer comprises forming the gate electrode to intersect with each of the at least two semiconductor layers of the multi-semiconductor layer that are connected to each other by the link.
19. The method of claim 2 , wherein each of the at least one or more slots of the gate electrode intersects with each of the at least two semiconductor layers of the multi-semiconductor layer that are connected to each other by the link.
20. The method of claim 9 , wherein the forming of the gate electrode intersecting with the multi-semiconductor layer forms the multiple gates of the thin film transistor.
21. The method of claim 9 , wherein the forming of the gate electrode intersecting with the multi-semiconductor layer comprises forming the gate electrode to intersect with each of the at least two semiconductor layers of the multi-semiconductor layer that are connected to each other by the link.
22. The method of claim 12 , wherein each of the at least one or more slots of the gate electrode intersects with each of the at least two semiconductor layers of the multi-semiconductor layer that are connected to each other by the link.