Semiconductor integrated circuit and manufacturing method
View Patent ↗In order to provide a semiconductor integrated circuit equipped with a clock distribution circuit that enables clock skew to be reduced without requiring great effort and without being affected by temperature variations or voltage variations, and a manufacturing method thereof, in a clock distribution circuit 1 installed in a semiconductor integrated circuit, part of the distribution path of a clock signal that passes from a first selector 11 of a first circuit block 10 that has many buffer stages via a first buffer stage 10 A is used, and a distribution path of a clock signal to a second buffer stage 20 A of a second circuit block 20 that has few buffer stages is constructed.
1. A semiconductor integrated circuit equipped with a clock distribution circuit comprising:
a first circuit block in which a plurality of first buffer stages are arranged according to a buffer tree structure and a clock signal output from a first selector is distributed to said plurality of first buffer stages; and
a second circuit block in which second buffer stages of fewer stages compared with said first circuit block are arranged according to a buffer tree structure and the clock signal output from said first selector is distributed to a second buffer stage via said first buffer stage and a second selector.
2. The semiconductor integrated circuit equipped with a clock distribution circuit according to claim 1 , wherein a delay value of a clock signal reaching a second buffer stage of a second circuit block from said first selector via said first buffer stage and second selector, and a delay value of a clock signal reaching a first buffer stage of a first circuit block from said first selector at an identical level to this second buffer stage, are equal.
3. A manufacturing method of a semiconductor integrated circuit equipped with a clock distribution circuit comprising:
a step of placing a first circuit block in which a plurality of first buffer stages are arranged according to a buffer tree structure and a clock signal output from a first selector is distributed to said plurality of first buffer stages;
a step of placing a second circuit block in which second buffer stages comprising fewer stages compared with said first circuit block are arranged according to a buffer tree structure and a clock signal output from a second selector is distributed to second buffer stages; and
a step of placing a connecting wire that supplies the clock signal from said first selector to said second selector via said first buffer stages.
4. The manufacturing method of a semiconductor integrated circuit equipped with a clock distribution circuit according to claim 3 , wherein said step of placing a connecting wire comprises:
a step of calculating a difference between a delay value of a clock signal reaching a second buffer stage of a second circuit block from said second selector and a delay value of a clock signal reaching a first buffer stage of said first circuit block from said first selector at an identical level to this first buffer stage, and;
a step of placing a connecting wire that equalizes said delay value difference between said first circuit block first buffer stage output and second selector input.