Method and system for blocking data in scan registers from being shifted out of a device
View Patent ↗Aspects of a method and system for blocking data in scan registers from being shifted out of a device may comprise preventing data intrusion in an integrated circuit by generating a device reset signal prior to entering scan mode. The method may further comprise detecting an attempt to enter said scan mode. The device reset signal may also be an internal reset signal. A subsequent device reset signal may be generated after entering scan mode. The subsequent device reset signal may be an internal pulse signal. The method may further comprise clearing stored data in an integrated circuit after generating a subsequent device reset signal.
1. A method for preventing data intrusion in an integrated circuit, the method comprising:
generating an internal reset signal based on an external reset signal prior to entering a scan mode, wherein said generated internal reset signal enables deletion of stored data within a chip device; and
generating a subsequent internal reset signal based on an external test mode signal, which configures said chip device for said entering said scan mode, wherein said generated subsequent internal reset signal enables deletion of said stored data.
2. The method according to claim 1 , comprising generating one or more time delayed versions of said external test mode signal based on an external clock signal.
3. The method according to claim 2 , comprising generating said internal reset signal based on said one or more time delayed versions of said external test mode signal and/or an external test enable signal.
4. The method according to claim 1 , comprising generating an asynchronous reset signal based on said internal reset signal and an internal pulse signal.
5. The method according to claim 4 , comprising generating a time delayed version of said asynchronous reset signal based on a time domain clock signal.
6. The method according to claim 5 , comprising generating a chip device reset signal based on said asynchronous reset signal, said time delayed version of said asynchronous reset signal and/or a scan testmode signal.
7. The method according to claim 6 , comprising deleting said stored data based on said generated chip device reset signal.
8. A system for preventing data intrusion in an integrated circuit, the system comprising:
one or more circuits that enable generation of an internal reset signal based on an external reset signal prior to entering a scan mode, wherein said generated internal reset signal enables deletion of stored data within a chip device; and
said one or more circuits enable generation of a subsequent internal reset signal based on an external test mode signal, which configures said chip device for said entering said scan mode, wherein said generated subsequent internal reset signal enables deletion of said stored data.
9. The system according to claim 8 , wherein said one or more circuits enable generation of one or more time delayed versions of said external test mode signal based on an external clock signal.
10. The system according to claim 9 , wherein said one or more circuits enable generation of said internal reset signal based on said one or more time delayed versions of said external test mode signal and/or an external test enable signal.
11. The system according to claim 8 , wherein said one or more circuits enable generation of an asynchronous reset signal based on said internal reset signal and an internal pulse signal.
12. The system according to claim 11 , wherein said subsequent device reset signal is an internal pulse signal wherein said one or more circuits enable generation of a time delayed version of said asynchronous reset signal based on a time domain clock signal.
13. The system according to claim 12 , wherein said one or more circuits enable generation of a chip device reset signal based on said asynchronous reset signal, said time delayed version of said asynchronous reset signal and/or a scan testmode signal.
14. The system according to claim 13 , wherein said one or more circuits enable deletion of said stored data based on said generated chip device reset signal.
15. A method for operation of an integrated circuit, the method comprising:
generating an internal reset signal prior to entering a scan mode;
generating a scan testmode signal by latching an external scan mode signal based upon said internal reset signal; and
generating a scan testmode delay signal based upon a delayed version of said scan testmode signal.
16. The method according to claim 15 , comprising generating an internal pulse signal based upon said scan testmode signal and said scan testmode delay signal.
17. The method according to claim 16 , comprising generating said internal pulse signal based on a logical exclusive-NOR operation on said scan testmode signal and said scan testmode delay signal.
18. A system for operation of an integrated circuit, the system comprising:
one or more circuits that enable generation of an internal reset signal prior to entering a scan mode;
said one or more circuits enable generation of a scan testmode signal by latching an external scan mode signal based upon said internal reset signal; and
said one or more circuits enable generation of a scan testmode delay signal based upon a delayed version of said scan testmode signal.
19. The system according to claim 18 , wherein said one or more circuits enable generation of an internal pulse signal based upon said scan testmode signal and said scan testmode delay signal.
20. The system according to claim 19 , wherein said one or more circuits enable generation of said internal pulse signal based on a logical exclusive-NOR operation on said scan testmode signal and said scan testmode delay signal.