Programmable phase shift and duty cycle correction circuit and method
View Patent ↗A phase shift and duty cycle correction circuit is disclosed herein as comprising a programmable digital to analog converter (DAC), a storage device (e.g., a capacitor), a charge sub-circuit and dump sub-circuit for charging and discharging the storage device, respectively, a comparator, and a clock driver circuit. A linearly increasing (or ramped) voltage waveform is generated within the storage device by the charging and discharging actions of the charge and dump sub-circuits; a periodic process which is controlled by opposite phases of the input clock. By programming the DAC control input to change the slicing threshold of the ramped waveform, the circuit and method described herein provides a means for programmable phase shifting and duty cycle correction.
1. A circuit configured for generating an output signal in response to an input signal, the circuit comprising:
a storage device configured for generating a linearly increasing voltage signal when charged;
series-coupled current source and switch further coupled in series with the storage device for charging the storage device when the switch is closed;
a programmable digital-to-analog converter (DAC) configured for generating an adjustable reference voltage;
a comparator having a pair of inputs, one coupled to the storage device and one to the programmable DAC, wherein the comparator is configured for transitioning the output signal from logic LOW to logic HIGH once the linearly increasing voltage exceeds the adjustable reference voltage, and wherein a phase difference between the input and output signals is determined, at least in part, by the adjustable reference voltage; and
a delay sub-circuit coupled for receiving the input signal and configured for generating a discharge signal on each rising edge of the input signal.
2. The circuit as recited in claim 1 , wherein the storage device comprises a capacitor.
3. The circuit as recited in claim 2 , wherein values associated with the capacitor and/or the current source can be adjusted for changing a slope of the linearly increasing voltage signal, and as a result, increasing or decreasing the phase difference between the input and output signals.
4. The circuit as recited in claim 2 , further comprising a storage means coupled to the programmable DAC for supplying an N-bit digital word thereto, wherein the number ‘N’ is selected from a range of integer values between about 2 and 8, and wherein the digital word is converted by the programmable DAC into an analog value representative of the adjustable reference voltage.
5. The circuit as recited in claim 4 , wherein said storage means is selected from a group of programmable devices comprising registers, counters and memory devices.
6. The circuit as recited in claim 4 , further comprising a discharging sub-circuit coupled in parallel to the storage device for discharging the storage device to ground upon receiving a second discharge signal.
7. The circuit as recited in claim 6 , wherein the discharging sub-circuit comprises a transistor, which when activated by the second discharge signal, resets the storage device to a ground potential.
8. The circuit as recited in claim 7 , wherein the second discharge signal is generated in response to a rising edge of a complementary input signal, which is received by a second circuit substantially identical to the circuit.
9. The circuit as recited in claim 8 , wherein the second circuit comprises:
a second delay sub-circuit coupled for receiving the complementary input signal and configured for generating the second discharge signal on each rising edge of the complementary input signal;
a second storage device configured for generating a second linearly increasing voltage signal when charged;
a second charging sub-circuit coupled in series with the second storage device for charging the second storage device in response to the rising edge of the complementary input signal;
a second discharging sub-circuit coupled in parallel to the second storage device for discharging the second storage device to ground upon receiving the first discharge signal from the first delay sub-circuit;
a second programmable digital-to-analog converter (DAC) configured for generating a second adjustable reference voltage; and
a second comparator having a pair of inputs, one coupled to the second storage device and one to the second programmable DAC, wherein the second comparator is configured for transitioning the output signal from logic HIGH to logic LOW once the second linearly increasing voltage exceeds the second adjustable reference voltage.
10. A circuit configured for generating an output signal from a pair of complementary input signals, the circuit comprising:
a first circuit block coupled for receiving a first one of the pair of complementary input signals, generating a first linearly increasing voltage in response to a rising edge of the first input signal, and transitioning the output signal from logic LOW to logic HIGH once the first linearly increasing voltage exceeds a first adjustable reference voltage set by the first circuit block;
a second circuit block, substantially identical to the first circuit block, wherein the second circuit block is coupled for receiving a second one of the pair of complementary input signals, generating a second linearly increasing voltage in response to a rising edge the second input signal, and transitioning the output signal from logic HIGH to logic LOW once the second linearly increasing voltage exceeds a second adjustable reference voltage set by the second circuit block; and
wherein at least one of the adjustable reference voltages set by the first and second circuit blocks can be adjusted to alter a duty cycle of the output signal and/or a phase difference between the input and output signals.
11. The circuit as recited in claim 10 , wherein the first circuit block comprises:
a first delay sub-circuit coupled for receiving the rising edge of the first input signal and configured for generating a first discharge signal;
a first storage device configured for generating the first linearly increasing voltage signal when charged;
a first charging sub-circuit coupled in series with the first storage device for charging the first storage device in response to the rising edge of the first input signal;
a first discharging sub-circuit coupled in parallel to the first storage device for discharging the first storage device to ground upon receiving a second discharge signal from the second circuit block;
a first programmable digital-to-analog converter (DAC) configured for generating the first adjustable reference voltage; and
a first comparator having a pair of inputs, one coupled to the first storage device and one to the first programmable DAC, wherein the first comparator is configured for transitioning the output signal from logic LOW to logic HIGH once the first linearly increasing voltage exceeds the first adjustable reference voltage.
12. The circuit as recited in claim 11 , wherein the second circuit block comprises:
a second delay sub-circuit coupled for receiving the rising edge of the second input signal and configured for generating the second discharge signal;
a second storage device configured for generating the second linearly increasing voltage signal when charged;
a second charging sub-circuit coupled in series with the second storage device for charging the second storage device in response to the rising edge of the second input signal;
a second discharging sub-circuit coupled in parallel to the second storage device for discharging the second storage device to ground upon receiving the first discharge signal from the first circuit block;
a second programmable digital-to-analog converter (DAC) configured for generating the second adjustable reference voltage; and
a second comparator having a pair of inputs, one coupled to the second storage device and one to the second programmable DAC, wherein the second comparator is configured for transitioning the output signal from logic HIGH to logic LOW once the second linearly increasing voltage exceeds the second adjustable reference voltage.
13. The circuit as recited in claim 12 , wherein the first and second circuit blocks each comprise a means for supplying the first and second programmable DACs with a pair of N-bit digital words associated with the first and second adjustable reference voltages.
14. The circuit as recited in claim 13 , wherein said means is selected from a group of programmable devices comprising registers, counters and memory devices.
15. The circuit as recited in claim 13 , wherein the output signal can be set to attain a 50% duty cycle, if each of said means is programmed with the same N-bit digital word, thereby causing the first and second programmable DACs to generate substantially identical first and second adjustable reference voltages.
16. The circuit as recited in claim 13 , wherein the output signal can be set to attain a duty cycle, which is substantially greater than or less than 50%, if said means are programmed with substantially different N-bit digital words, thereby causing the first and second programmable DACs to generate substantially different first and second adjustable reference voltages.
17. The circuit as recited in claim 13 , wherein the phase difference between the input and output signals is determined by a slope of the first linearly increasing voltage signal and the first adjustable reference voltage.
18. The circuit as recited in claim 17 , wherein the first storage device comprises a capacitor, wherein the first charging sub-circuit comprises a current source, and wherein values associated with the capacitor and/or the current source can be adjusted for changing the slope of the first linearly increasing voltage signal, and as a result, increasing or decreasing the phase difference between the input and output signals.
19. A method for generating an output signal from a pair of complementary input signals, the method comprising:
producing a first linearly increasing voltage signal upon receiving a rising edge of a first one of the pair of complementary input signals;
generating a logic HIGH output signal once the first linearly increasing voltage signal exceeds a first adjustable reference voltage;
producing a second linearly increasing voltage signal upon receiving a rising edge of a second one of the pair of complementary input signals;
generating a logic LOW output signal once the second linearly increasing voltage signal exceeds a second adjustable reference voltage; and
setting the first and second adjustable reference voltages to control a duty cycle and phase shift amount associated with the output signal.
20. The method as recited in claim 19 , wherein the step of setting comprises selecting substantially identical first and second adjustable reference voltages to provide the output signal with approximately 50% duty cycle.
21. The method as recited in claim 19 , wherein the step of setting comprises selecting first and second adjustable reference voltages, which are substantially different from one another, to provide the output signal with a duty cycle that is substantially greater or less than 50%.
22. The method as recited in claim 19 , wherein the step of setting comprises increasing/decreasing the first adjustable reference voltage to increase/decrease the phase shift amount associated with the output signal.
23. The method as recited in claim 19 , wherein the steps of producing the first and second linearly increasing voltage signals each comprise supplying a current to a capacitive storage device.
24. The method as recited in claim 23 , further comprising adjusting one or more values associated with the current and the capacitive storage device for changing the slope of at least one of the linearly increasing voltage signals, and as a result, altering the duty cycle and/or phase shift amount associated with the output signal.
25. The method as recited in claim 24 , wherein the step of adjusting also enables a frequency of the output signal to be set equal to, or different than, a frequency of the complementary input signals.