Method of fabricating thin film transistor

1. A method of fabricating a thin film transistor, comprising:

preparing an insulating substrate;

forming a first amorphous silicon layer on the substrate;

forming a diffusion barrier layer pattern on a portion of the first amorphous silicon layer;

forming a second amorphous silicon layer over the diffusion barrier layer;

forming a metal silicide layer on the second amorphous silicon layer; and

heat-treating the substrate to crystallize the first and second amorphous silicon layers, wherein the heat-treating forms a first polysilicon layer on regions of the substrate where there is no diffusion barrier layer pattern and a second polysilicon layer on regions of the substrate covered by the diffusion barrier layer pattern.

2. The method of claim 1 , further comprising, after heat-treating the substrate,

etching the metal silicide layer and the crystallized second amorphous silicon layer covering the diffusion barrier layer pattern;

removing the diffusion barrier layer pattern;

patterning the first polysilicon layer and the second polysilicon layer to form a semiconductor layer; and

sequentially forming a gate insulating layer, a gate electrode, an interlayer insulator, and source and drain electrodes over the semiconductor layer.

3. The method of claim 2 , wherein the second polysilicon layer is crystallized by a MILC technique and the first polysilicon layer is crystallized by a MIC technique.

4. The method of claim 2 , wherein a mask used to form the diffusion barrier layer pattern is identical to that used to form the semiconductor layer.

5. The method of claim 1 , further comprising, after heat-treating the substrate;

etching the metal silicide layer and the first polysilicon layer;

etching the diffusion barrier layer pattern to form a semiconductor layer; and

sequentially forming a gate insulating layer, a gate electrode, an interlayer insulator, and source and drain electrodes over the semiconductor layer.

6. The method of claim 5 , wherein the second polysilicon layer is crystallized by a MILC technique.

7. The method of claim 1 , further comprising, after heat-treating the substrate,

etching the metal silicide layer and the crystallized second amorphous silicon layer covering the diffusion barrier layer pattern;

patterning the first polysilicon layer and the second polysilicon layer to form a semiconductor layer and a first gate insulating layer; and

sequentially forming a second gate insulating layer, a gate electrode, an interlayer insulator, and source and drain electrodes over the substrate.

8. The method of claim 7 , wherein the first gate insulating layer is formed of the diffusion barrier layer pattern.

9. The method of claim 7 , wherein the second polysilicon layer is crystallized by a MILC technique and the first polysilicon layer is crystallized by a MIC technique.

10. The method of claim 1 , further comprising, after heat-treating the substrate,

etching the metal silicide layer and the first polysilicon layer to form a first gate insulating layer and a semiconductor layer; and

sequentially forming a second gate insulating layer, a gate electrode, an interlayer insulator, and source and drain electrodes over the substrate.

11. The method of claim 10 , wherein the first gate insulating layer is formed of the diffusion barrier layer pattern.

12. The method of claim 10 , wherein the second polysilicon layer is crystallized by a MILC technique.

13. The method of claim 1 , wherein the first amorphous silicon layer has a thickness from 400 Å to 600 Å.

14. The method of claim 1 , wherein the second amorphous silicon layer has a thickness from 500 Å to 1,500 Å.

15. The method of claim 1 , wherein the heat-treatment process is performed at a temperature from 400° C. to 1,300° C.

16. The method of claim 1 , wherein the heat-treatment process is performed at a temperature from 400° C. to 700° C.

17. The method of claim 1 , wherein the metal silicide layer is formed of a compound of a silicon and a metal selected from the group consisting of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Cr, Ru, Rh, Cd, and Pt.

18. The method of claim 1 , wherein the metal silicide layer is a nickel silicide layer.

19. The method of claim 1 , wherein the diffusion barrier layer pattern is a silicon oxide layer or a silicon nitride layer and has a single-layer or multi-layer structure.

20. The method of claim 1 , wherein the diffusion barrier layer pattern is a pattern for preventing the metal silicide layer or a crystallinity of the first polysilicon layer from being diffused or transferred into the second polysilicon layer below the diffusion barrier layer pattern.