TAP time division multiplexing with scan test
View Patent ↗An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode.
1. An integrated circuit comprising:
a plurality of portions, each portion including test control circuitry; and
at least one test input arranged to receive test signals,
one or more of said test control circuitry having a plurality of test modes comprising a structural test mode and a debug mode, wherein at least one of said test modes one or more of said plurality of portions are testable, and wherein said test control circuitry has a reset mode which has priority over said test modes and said structural test mode has priority over said debug mode wherein said debug mode comprises a multiplexer mode.
2. The circuit of claim 1 , wherein said reset mode comprises a bypass mode.
3. The circuit of claim 1 , wherein said reset mode has the highest priority of any modes of said integrated circuit.
4. The circuit of claim 1 , wherein said test modes comprise a scan test mode.
5. The circuit of claim 1 , wherein one of said test control circuitry comprises master test circuitry.
6. The circuit of claim 5 , wherein said master test circuitry is arranged to test at least one other of the other portions of circuit.
7. The circuit of claim 5 , wherein said master test circuitry is arranged to test all of the other portions of said circuit.
8. The circuit of claim 1 , wherein said master test circuitry comprises a TAP controller.
9. The circuit of claim 1 , wherein said test control circuitry comprises a TAP multiplexer for multiplexing input and/or output test data to/from a plurality of test circuitry.
10. The circuit of claim 9 , wherein said TAP multiplexer comprises bypass combinatorial logic and sequential logic.
11. The circuit of claim 10 , wherein said sequential logic is bypassed in said bypass mode.
12. The circuit of claim 10 , wherein the sequential logic is tested via said master test circuitry.
13. The circuit of claim 1 , wherein said structural test mode takes priority over a multiplexer mode in which said one of said test circuitry provides a multiplexer function.
14. The circuit of claim 1 , wherein the integrated circuit comprises a selection by sequence mode.
15. An integrated circuit comprising:
a plurality of portions, each portion including test control circuitry; and
at least one test input arranged to receive test signals, one or more of said test control circuitry having a plurality of test modes comprising a structural test mode and a debug mode, wherein said structural test mode has priority over said debug mode and said debug mode comprises a multiplexer mode, wherein in at least one of said test modes on or more of said plurality of portions are testable, wherein said test control circuitry has a reset mode which has priority over said test modes so that if the chip powers up in a test mode a reset will cause the test mode to be exited and wherein said test mode comprises a multiplexer mode.
16. The circuit of claim 15 , wherein said reset mode comprises a bypass mode.
17. The circuit of claim 15 , wherein said reset mode has the highest priority of any modes of said integrated circuit.
18. The circuit of claim 15 , wherein said test modes comprise a scan test mode.
19. The circuit of claim 15 , wherein one of said test control circuitry comprises master test circuitry.
20. The circuit of claim 19 , wherein said master test circuitry comprises a TAP controller.