Thin film transistor with improved junction region
View Patent ↗A thin film transistor and method of fabricating the same are provided. In the thin film transistor, a seed or a grain boundary exists in a semiconductor layer pattern but not in a junction region. The method includes forming a semiconductor layer pattern. Forming the semiconductor layer pattern includes: forming and patterning a first capping layer on an amorphous silicon layer; forming a second capping layer on the first capping layer pattern; forming a metal catalyst layer on the second capping layer; diffusing the metal catalyst; and crystallizing the amorphous silicon layer to form a polysilicon layer. Therefore, it is possible to prevent that a trap is generated in the junction region, thereby obtaining improved and uniform characteristics of the device.
1. A thin film transistor comprising:
a substrate;
a semiconductor layer pattern formed on the substrate wherein the semiconductor layer pattern includes a source region, a drain region, and a channel;
a gate insulating layer formed on the semiconductor layer pattern; and
a gate electrode formed on the gate insulating layer,
wherein a seed or a grain boundary exists in the semiconductor layer pattern but a junction region in the semiconductor layer pattern wherein the source region and the channel meet and the drain region and the channel meet does not have a grain boundary, and does not have a seed, the seed being formed of a metal silicide, and
wherein the seed is formed within 1 to 3 μm of the junction region in a direction of a contact hole.
2. The thin film transistor according to claim 1 , wherein the seed or the grain boundary in the semiconductor layer pattern exists in an active region of the semiconductor layer pattern.
3. The thin film transistor according to claim 1 , wherein the junction region is formed within 1 μm of the junction region to the source region or the drain region.
4. The thin film transistor according to claim 1 , wherein the junction region has a crystallization ratio of 0.7 to 0.9.
5. The thin film transistor according to claim 1 , further comprising a buffer layer interposed between the substrate and the semiconductor layer pattern.
6. The thin film transistor according to claim 5 , wherein the buffer layer is formed of any one of a silicon nitride layer and a silicon oxide layer.
7. The thin film transistor according to claim 1 , wherein the thin film transistor is used in a liquid crystal device or an organic light emitting diode.