Method for forming dual gate electrodes using damascene gate process
View Patent ↗A method for forming dual gate electrodes using a damascene gate process is disclosed. A disclosed method comprises: growing a first gate oxide layer on a semiconductor substrate; performing a thermal treatment for a first gate oxide layer; removing a predetermined part of the first gate oxide layer until the top surface of the semiconductor substrate is exposed; growing a second gate oxide layer as a thin oxide layer on the exposed semiconductor substrate, thereby making the first gate oxide layer as a thick oxide layer; depositing polysilicon on the entire surface of the semiconductor substrate and forming dummy gates through a photolithography and an etching processes; forming sidewall spacers on the lateral faces of the dummy gates; forming source and drain regions in the substrate under both sides of the dummy gates; removing the dummy gates and the second gate oxide layer; forming an insulating layer where the second gate oxide layer is removed; performing a thermal treatment for the insulating layer; filling polysilicon for gate electrodes where the dummy gates were removed; and planarizing the resulting structure until the gate electrodes are exposed.
1. A method for fabricating dual gate electrodes comprising:
growing a first gate oxide layer on a semiconductor substrate;
performing a thermal treatment for the first gate oxide layer;
removing a part of the first gate oxide layer to expose a surface of the semiconductor substrate;
growing a second gate oxide layer as a thin oxide layer over the exposed surface of the semiconductor substrate and the first gate oxide layer;
depositing a polysilicon layer over the entire surface of the semiconductor substrate;
etching the polysilicon layer to form at least a first dummy gate on the first gate oxide layer and at least a second dummy gate on the second gate oxide layer;
forming sidewall spacers on the lateral faces of the first and second dummy gates;
forming source and drain regions in the semiconductor substrate on both sides of the first and second dummy gates;
removing the first and second dummy gates and the second gate oxide layer between the sidewall spacers;
forming an insulating layer where the second gate oxide layer is removed;
performing a thermal treatment for the insulating layer;
filling polysilicon for gate electrodes where the dummy gates are removed; and
planarizing the polysilicon for gate electrodes to form gate electrodes.
2. A method as defined by claim 1 , wherein the thermal treatment for the first gate oxide layer is performed under a N 2 atmosphere.
3. A method as defined by claim 1 , wherein removing the second gate oxide layer accompanies removing a predetermined thickness of the first gate oxide layer.
4. A method as defined by claim 1 , wherein the insulating layer is made of silicon oxide or a material with a high dielectric constant.
5. A method as defined by claim 4 , wherein the material with a high dielectric constant is selected from the group consisting of TaO 5 , TiO 2 and ITO.
6. A method as defined by claim 1 , wherein the insulating layer is formed to have a thickness equal to that of the first gate oxide layer.
7. A method as defined by claim 1 , wherein the thermal treatment for the insulating layer is performed at a temperature about 600°.
8. A method as defined by claim 1 , wherein planarizing the polysilicon for gate electrodes comprises performing a CMP process.