Dynamic random access memory having at least two buffer registers and method for controlling such a memory
A dynamic random access memory circuit including a memory plane composed of an array of memory cells arranged in lines and columns, and a line decoder, each line of the memory plane corresponding to a page of words. Two buffer registers are coupled with the memory plane for reading words in a page of the memory and for writing new words to a page of the memory, and the registers are used alternatively to access this memory plane. The buffer registers are dual-port memories and, moreover, the memory has an error correcting circuit allowing read-modify-write cycles applied to a group of n words within the same page. Whereby the reliability of the memory circuit is substantially increased and, moreover, an alternative solution to burn-in can even be offered. The invention also provides a method for controlling a dynamic memory having an error correcting code mechanism.
1. A dynamic random access memory circuit comprising:
a memory plane composed of an array of memory cells arranged in lines and columns, and a line decoder, each line of said memory plane corresponding to a page of words;
at least first and second buffer registers coupled with the memory plane allowing reading of words of a memory page and writing of new words to a page of the memory plane, said first and second buffer registers being used alternatively to access said memory;
circuits associated with said first and second buffer registers in order to allow a simultaneous submission of a read column address and a write column address;
an error correcting mechanism applied to word groups in order to reduce a silicon surface allocated to the error correcting mechanism;
an error correcting circuit connected to an output of said at least first and second buffer registers and based on a correcting code applied to a group of n words constituting a sub-assembly of said page;
a register connected to an output of said error correcting circuit to store said group of n words, after correction;
an array of multiplexers for modifying a word within said group; and
an encoder circuit for recomputing a new correcting code based on said modified group before storage thereof in one of said buffer registers.
2. The memory circuit according to claim 1 wherein the number of buffer registers is set to two, said buffer registers being usable indifferently for reading and writing and ensuring read-modify-write cycles to access the memory plane.
3. The memory circuit according to claim 1 further comprising:
an interface circuit for receiving a memory access request comprising at least a page address and a column address, a read and write signal and, in the event of writes, data to be written;
a circuit for comparing the page address of the current request with a page address of a preceding request;
a circuit for storing the address of the current page it is different from the page address of the preceding page; and
a circuit for causing a new access to the memory plane when the current page is different from the preceding page.
4. The memory circuit according to claim 1 wherein each page has a size of 1024 bits and wherein said encoder circuit and decoder circuit operate on 128-bit word groups.
5. A memory circuit comprising:
an array of memory cells arranged in lines and columns, and a line decoder, each line of said memory plane corresponding to a page of words; and
at least first and second buffer registers coupled with the array of memory cells for reading words of a page of the memory and writing new words to a page of the memory, said first and second buffer registers being used alternatively to access said memory; wherein said at least first and second buffer registers are mounted as dual-port memories allowing writing and simultaneous reading;
an error correcting circuit coupled to an output of said at least first and second buffer registers and based on a correcting code applied to a group of n words constituting a sub-assembly of said page;
a register connected to an output of said error correcting circuit for storing said group of n words after correction;
a set of multiplexers for modifying a word within said group; and
an encoder circuit for recomputing a new correcting code based on said modified group before storage thereof in one of said buffer registers.