Applications of cascading DSP slices
In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.
1. An integrated circuit comprising:
a first digital signal processing (DSP) block, comprising a first hardwired multiplier coupled to a first hardwired adder; and
a second DSP block, comprising a second hardwired multiplier coupled to a second hardwired adder via a programmable multiplexer circuit, wherein the programmable multiplexer circuit is dynamically configurable during operation of the integrated circuit; and
wherein the first hardwired adder is coupled to the programmable multiplexer circuit, wherein the programmable multiplexer circuit is controlled by an opmode register that is writable during operation of the integrated circuit, wherein the opmode register is a register within the integrated circuit that is independent of configuration memory of the integrated circuit.
2. The integrated circuit of claim 1 further comprising a plurality of first-in-first-out (FIFO) queues coupled in series, wherein a first FIFO of the plurality of FIFO queues is coupled to the first hardwired multiplier and a second FIFO of the plurality of FIFO queues is coupled to the second hardwired multiplier.
3. The integrated circuit of claim 1 further comprising a plurality of shift registers coupled in series, wherein a first register coupled to a first shift register of the plurality of shift registers is coupled to the first hardwired multiplier and a second register coupled to a second shift register of the plurality of shift registers is coupled to the second hardwired multiplier.
4. The integrated circuit of claim 1 wherein the opmode register is clocked at a frequency that is different than a frequency of a configuration clock that clocks the configuration memory, wherein the opmode register is loaded with data specifying a mode of operation in an amount of time that is less than one configuration clock period.
5. The integrated circuit of claim 1 further comprising a shifter coupled between the first hardwired adder and the programmable multiplexer circuit.
6. An integrated circuit comprising:
a first digital signal processing (DSP) block, comprising a first hardwired multiplier coupled to a first hardwired adder; and
a second DSP block, comprising a programmable multiplexer circuit coupled to a second hardwired adder; and
wherein the first hardwired adder is coupled to the programmable multiplexer circuit, wherein the programmable multiplexer circuit is selectively configurable according to a register within the integrated circuit that is writable during operation of the integrated circuit thereby dynamically reconfiguring the programmable multiplexer circuit, wherein the register is independent of configuration memory of the integrated circuit.
7. A cascade digital signal processing (DSP) circuit for providing a multiplexer comprising:
a first DSP block, comprising a first programmable multiplexer circuit coupled to a first hardwired adder; and
a second DSP block, comprising a second programmable multiplexer circuit coupled to a second hardwired adder; and
wherein the first hardwired adder is coupled to the second programmable multiplexer circuit, wherein the programmable multiplexer circuit is selectively configurable according to a register within the integrated circuit that is writable during operation of the integrated circuit thereby dynamically reconfiguring the programmable multiplexer circuit, wherein the register is independent of configuration memory of the integrated circuit.
8. An integrated circuit comprising:
a first digital signal processing (DSP) block, comprising a first hardwired multiplier coupled to a first hardwired adder via a first programmable multiplexer circuit; and
a second DSP block, comprising a second hardwired multiplier coupled to a second hardwired adder via a second programmable multiplexer circuit; and
wherein the first hardwired adder is coupled to the second programmable multiplexer circuit, wherein the first programmable multiplexer circuit and the second programmable multiplexer circuit are dynamically configurable during operation of the integrated circuit, wherein the plurality of multiplexers are controlled by an opmode register, wherein the opmode register is a register within the integrated circuit that is independent of configuration memory of the integrated circuit.
9. The integrated circuit of claim 8 wherein the first programmable multiplexer circuit comprises a plurality of multiplexers.
10. The integrated circuit of claim 9 wherein the plurality of multiplexers comprise X, Y and Z multiplexers.
11. The integrated circuit of claim 8 wherein the integrated circuit is a programmable logic device (PLD).
12. The integrated circuit of claim 8 wherein the opmode register is clocked at a frequency that is different than a frequency of a configuration clock that clocks the configuration memory, wherein the opmode register is loaded with data specifying a mode of operation in an amount of time that is less than one configuration clock period.
13. An integrated circuit for performing digital signal processing operations, comprising:
a plurality of digital signal processing slices, wherein each slice comprises a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and
means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations dynamically during operation of the integrated circuit,
wherein a slice of the plurality of digital signal processing slices is programmed to perform a first function at a first time and is re-programmed to perform a second function at a second time according to an opmode register that is clocked at a frequency that is different than a frequency of a configuration clock that clocks configuration memory of the integrated circuit, wherein a difference between the second time and the first time is less than one configuration clock period.
14. The integrated circuit of claim 13 wherein the mathematical operations include finite impulse response (FIR) filtering.
15. The integrated circuit of claim 14 wherein the FIR filtering includes filtering operations selected from a group consisting of decimating, interpolating, and folding.
16. The integrated circuit of claim 13 wherein the mathematical operations include multiplexing, barrel shifting, counting, adding, subtracting, multiplying, dividing, accumulating, multiply/accumulating, and multirate filtering.