Thin film transistor array substrate and fabricating method thereof
View Patent ↗A thin film transistor array substrate includes a first conductive pattern group including a gate electrode of a thin film transistor and a gate line connected to the gate electrode; a semiconductor pattern defining a channel of the thin film transistor; a second conductive pattern group including source and drain electrodes of the thin film transistor and a data line crossing the gate line, a pixel area being defined by the data line crossing the gate line; a third conductive pattern group having a pixel electrode connected to the thin film transistor; and at least one dummy pattern disposed between at least one of the first to third conductive pattern groups and an adjacent one of the semiconductor patterns.
1. A method of fabricating a thin film transistor array substrate, comprising the steps of:
forming a first conductive pattern group on a substrate including at least one gate electrode of a thin film transistor, at least one gate line connected to the gate electrode, a common line and a plurality of common electrodes extending in opposing directions from the common line, the common line formed across a pixel area in a direction parallel to the gate line;
forming a second conductive pattern group on the substrate including source and drain electrodes of the thin film transistor, and at least one data line crossing the gate line adjacent to the pixel area; and
forming at least one pixel electrode connected to the drain electrode in the pixel area, the pixel electrode including a horizontal pixel electrode portion overlapping the common line and a plurality of vertical pixel electrode potions extending in opposing directions from the horizontal pixel electrode portion,
wherein the pixel electrode is connected to the drain electrode through a contact hole formed at the horizontal pixel electrode portion.
2. The method according to claim 1 , wherein a storage capacitor is formed in the overlapped portion of the horizontal pixel electrode portion, the drain electrode, and the common line.
3. The method according to claim 1 , wherein the step of forming the first conductive pattern group includes the steps of:
depositing a gate metal layer on the substrate, and
patterning the gate metal layer using a first soft mold.
4. The method according to claim 1 , further comprising the steps of:
forming an amorphous silicon layer over the first conductive pattern group;
forming an n+ amorphous silicon layer over the amorphous silicon layer; and
patterning the amorphous silicon layer and the n+ amorphous silicon layer using a second soft mold to form a semiconductor pattern.
5. The method according to claim 1 , wherein the step of forming the second conductive pattern group includes the steps of:
depositing a data metal layer on the substrate, and
patterning the data metal layer using a third soft mold.
6. The method according to claim 1 , further comprising the step of:
forming a protective film on the substrate over the second conductive pattern group; and
patterning the protective film using a fourth soft mold to form at least one contact hole through which the pixel electrode is connected to the drain electrode.
7. The method according to claim 1 , wherein the step of forming the pixel electrode includes the steps of:
forming a transparent conductive film on the substrate, and
patterning the transparent conductive film using a fifth soft mold.