Resistor-less accurate low voltage detect circuit and method for detecting a low voltage condition

1. A low voltage detect circuit configured for detecting when an external voltage (Vext) drops below a predetermined minimum voltage and for generating a detect signal in response thereto, wherein the generation of the detect signal is dependent on a threshold voltage difference between a non-zero threshold transistor having a substantially non-zero threshold voltage, and a zero threshold transistor having a threshold voltage substantially equal to zero.

2. The circuit as recited in claim 1 , wherein the non-zero threshold transistor comprises a first threshold voltage (V TH — NZ ) within a range of about −1.5V to about −0.5V or within a range of about 0.5V to about 1.5V, and wherein the zero threshold transistor comprises a second threshold voltage (V TH — z) within a range of about − 0.4V to about +0.4V.

3. The circuit as recited in claim 2 , wherein the non-zero threshold transistor comprises a first threshold voltage (V TH — NZ ) within a range of about 0.8V to about 0.9V, and wherein the zero threshold transistor comprises a second threshold voltage (V TH — Z ) within a range of about −0.2V to about +0.2V.

4. The circuit as recited in claim 2 , wherein the zero and non-zero threshold transistors each comprise P-channel Metal Oxide Semiconductor (PMOS) transistors.

5. The circuit as recited in claim 2 , wherein the zero and non-zero threshold transistors each comprise N-channel Metal Oxide Semiconductor (NMOS) transistors.

6. The circuit as recited in claim 5 , comprising substantially no resistors.

7. The circuit as recited in claim 6 , comprising:

a first sub-circuit configured to generate voltage signal, A, which is substantially less than or equal to the external voltage;

a second sub-circuit configured to generate voltage signal, B, which is substantially equal to a threshold voltage difference between at least one non-zero threshold transistor and at least one zero threshold transistor; and

a comparator configured to compare voltage signals A and B, and to generate the detect signal when voltage signal A becomes less than or equal to voltage signal B.

8. The circuit as recited in claim 7 , wherein the first sub-circuit comprises:

a first non-zero threshold transistor coupled between a power supply node and a first input of the comparator, wherein the first non-zero threshold transistor is diode-connected and configured for receiving the external voltage at a gate terminal thereof; and

a first biasing stage coupled in series with the first non-zero threshold transistor between the first input of the comparator and ground.

9. The circuit as recited in claim 8 , wherein the second sub-circuit comprises:

a pair of zero-threshold transistors coupled in series between the power supply node and a second input of the comparator; and

a second biasing stage coupled in series with the pair of zero-threshold transistors between the second input of the comparator and ground.

10. The circuit as recited in claim 9 , wherein the pair of zero-threshold transistors comprises a first zero-threshold transistor and a second zero-threshold transistor, and wherein:

the first zero-threshold transistor is coupled between the power supply node and the second zero-threshold transistor, wherein the first zero-threshold MOS transistor is configured for receiving a turn-on voltage at a gate terminal thereof; and

the second zero-threshold transistor is coupled between the first zero-threshold transistor and the second input of the comparator, wherein the second zero-threshold transistor is diode-connected and configured for receiving a threshold voltage difference between a non-zero threshold transistor and a zero threshold transistor, at a gate terminal thereof.

11. The circuit as recited in claim 9 , wherein the first and second biasing stages each comprise a non-zero threshold transistor coupled for receiving a bias voltage at a gate terminal thereof.

12. The circuit as recited in claim 11 , wherein the circuit comprises a standby current consumption no greater than 120 nano-amperes (nA).

13. The circuit as recited in claim 12 , wherein a trip point of the comparator has a maximum variation of +/−100 milli-volts (mV) across process, voltage, and temperature (PVT) corners.

14. The circuit as recited in claim 13 , wherein the predetermined minimum voltage is approximately equal to twice the threshold voltage difference between a non-zero threshold transistor and a zero threshold transistor, or 2 times (V TH — NZ −V TH — Z ).

15. The circuit as recited in claim 13 , wherein the predetermined minimum voltage is approximately equal to (2+N) times (V TH — NZ −V TH — Z ) if:

the first sub-circuit further comprises an additional N-number of diode-connected non-zero threshold transistors, which are coupled in series between the first non-zero threshold transistor and the first input of the comparator;

the second sub-circuit further comprises an additional N-number of diode-connected zero threshold transistors, which are coupled in series between the second zero threshold transistor and the second input of the comparator; and

wherein the number N is selected from a range of integer values comprising about 1 to about 5.

16. The circuit as recited in claim 13 , wherein the predetermined minimum voltage is approximately equal to (V TH — NZ −V TH — Z ) if:

the first non-zero threshold transistor is eliminated from the first sub-circuit and the power supply node is directly coupled to the first input of the comparator; and

the second zero threshold transistor is eliminated from the second sub-circuit and the first zero threshold transistor is coupled between the power supply node and the second input of the comparator.

17. A memory system comprising a power regulator with a low voltage detect circuit for detecting when an external voltage drops below a predetermined minimum voltage, wherein the low voltage detect circuit comprises:

a first sub-circuit configured to generate voltage signal, A, which is substantially less than or equal to the external voltage;

a second sub-circuit configured to generate voltage signal, B, which is substantially equal to a threshold voltage difference between at least one transistor with a substantially non-zero threshold voltage and at least one additional transistor with a threshold voltage close to zero; and

a comparator configured to compare voltage signals A and B, and to generate the detect signal when voltage signal A becomes less than or equal to voltage signal B.

18. The memory system as recited in claim 17 , wherein the low voltage detect circuit comprises substantially no resistors or voltage generation circuits.

19. A method for detecting a low-voltage condition and for generating a detect signal in response thereto, the method comprising:

generating a first voltage signal, A, which is substantially less than or equal to an external voltage;

generating a second voltage signal, B, which is substantially equal to a threshold voltage difference between at least one non-zero threshold transistor having a substantially non-zero threshold voltage and at least one zero threshold transistor having a threshold voltage close to zero;

comparing voltage signals A and B and generating the detect signal when voltage signal A becomes less than or equal to voltage signal B, signifying the low-voltage condition.

20. The method as recited in claim 19 , wherein said step of generating a first voltage signal, A, comprises establishing a difference between the external voltage and a threshold voltage of at least one non-zero threshold transistor.

21. The method as recited in claim 19 , wherein said step of generating a second voltage signal, B, comprises establishing a threshold voltage difference between one non-zero threshold transistor and at least two zero threshold transistors.

22. The method as recited in claim 19 , wherein said steps of generating a first and second voltage signal are performed without using any resistors or reference voltage generation circuits.