IP Library Granted Patent US 7,702,058
Granted Patent B2
US 7,702,058 · App. 11/021,128 · Granted Apr 20, 2010

Data recovery method and module

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Quick Facts
Patent No.
US 7,702,058
App. No.
11/021,128
Granted
Apr 20, 2010
Kind
B2
Abstract

A method and apparatus for recovering data by a digital audio interface begins by receiving a stream of biphase encoded data. The processing continues by determining whether a next transition of a frame of the plurality of frames occurs during a first, second, or third time window after a preceding transition of the frame. When the next transition occurs during the second predetermined time, the digital audio interface synchronizes to a data rate of the stream of biphase encoded data based on the next transition and the preceding transition. If, the next transition occurs during the first or third predetermined windows, the digital audio interface synchronizes to a data rate of the stream of biphase encoded data based on the preceding transition edge and a subsequent transition. When the transition occurs during the third time window, the biphase encoding is violated, which indicates that a preamble is being received.

Claims (29)

1. A method for data recovery, the method comprises the steps of:

a) receiving a stream of biphase encoded data, wherein the stream of biphase encoded data includes a plurality of frames;

b) determining whether a next transition of a frame of the plurality of frames occurs during a first, second, or third time window after a preceding transition of the frame by:

counting a number of clock cycles of an output of a phase locked loop that occur between the preceding transition and the next transition;

determining that the next transition occurs during the first time window when the number of clock cycles is in a first range of clock cycles;

determining that the next transition occurs during the second time window when the number of clock cycles is in a second range of clock cycles; and

determining that the next transition occurs during the third time window when the number of clock cycles is in a third range of clock cycles;

c) synchronizing to a data rate of the stream of biphase encoded data based on the next transition and the preceding transition when the next transition occurs during the second time window;

d) synchronizing to the data rate of the stream of biphase encoded data based on the preceding transition and a subsequent transition when the next transition occurred during the first or the third time window;

e) adjusting a dynamic divider based on the data rate and an output of a phase locked loop to produce a divided value, wherein the adjusting the dynamic divider further comprises: determining a current count based on a number of clock cycles of the output of the phase locked loop that occur during a frame of the stream of biphase encoded data; comparing the current count with a stored minimum count; and decrementing the stored minimum count when the current count compares unfavorably to the stored minimum count; and

f) generating a recovered data clock signal based on the output of the phased locked loop and the divided value.

2. The method of claim 1 further comprises, prior to the phase locked loop being locked:

determining whether a stored minimum count is less than a predetermined value;

decreasing rate of the phase locked loop when the stored minimum count is less than the predetermined value.

3. The method of claim 2 further comprises, prior to the phase locked loop being locked:

determining whether the stored minimum count is greater than a predetermined value; and

increasing rate of the phase locked loop when the stored minimum count is greater than the predetermined value.

4. A data recovery module comprises:

receiving module operably coupled to receive a stream of biphase encoded data, wherein the stream of biphase encoded data includes a plurality of frames, wherein the receiving module includes:

a phase locked loop having an adjustable dynamic divider that is adjusted based on the data rate and an output of the phase locked loop to produce a divider wherein the adjustable dynamic divider is adjusted by, determining a current count based on a number of clock cycles of the output of the phase locked loop that occur during a frame of the stream of biphase encoded data, comparing the current count with a stored minimum count, and decrementing the stored minimum count when the current count compares unfavorably to the stored minimum count: and

clock recovery module operably coupled to produce a recovered data clock based on the output of the phased locked loop and the divider;

determining module operably coupled to whether a next transition of a frame of the plurality of frames occurs during a first, second, or third time window after a preceding transition of the frame, wherein the determining module functions to count a number of clock cycles of an output of a phase locked loop that occur between the preceding transition and the next transition, determine that the next transition occurs during the first time window when the number of clock cycles is in a first range of clock cycles, determine that the next transition occurs during the second time window when the number of clock cycles is in a second range of clock cycles, and determine that the next transition occurs during the third time window when the number of clock cycles is in a third range of clock cycles;

synchronizing module operably coupled to synchronize to a data rate of the stream of biphase encoded data based on the next transition and the preceding transition when the next transition occurred during the second time window and to synchronize the data rate of the stream of biphase encoded data based on the preceding transition and a subsequent transition when the next transition occurred during the first or the third time window.

5. The data recovery module of claim 4 , wherein the phase locked loop functions to, prior to the phase locked loop being locked:

determine whether a stored minimum count is less than a predetermined value;

decrease rate of the phase locked loop when the stored minimum count is less than the predetermined value.

6. The data recovery module of claim 5 , wherein the phase locked loop further functions to, prior to the phase locked loop being locked:

determine whether the stored minimum count is greater than a predetermined value; and

increase rate of the phase locked loop when the stored minimum count is greater than the predetermined value.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Jun 6, 2017
From: SILICON VALLEY BANK
To: TEMPO SEMICONDUCTOR, INC.
Reel/Frame 042614/0869 →
SECURITY INTEREST Recorded Feb 18, 2015
From: TEMPO SEMICONDUCTOR, INC.
To: SILICON VALLEY BANK
Reel/Frame 035033/0681 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2014
From: INTEGRATED DEVICE TECHNOLOGY, INC.
To: STRAVELIS,INC.
Reel/Frame 032662/0007 →
CHANGE OF NAME Recorded Apr 13, 2014
From: STRAVELIS, INC.
To: TEMPO SEMICONDUCTOR, INC.
Reel/Frame 032672/0966 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 21, 2008
From: SIGMATEL, INC.
To: INTEGRATED DEVICE TECHNOLOGY, INC.
Reel/Frame 020828/0913 →