IP Library Granted Patent US 7,151,681
Granted Patent B2
US 7,151,681 · App. 11/022,167 · Granted Dec 19, 2006

Multiple-sampling circuit for measuring reflected voltage and discharge time of a transformer

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Quick Facts
Patent No.
US 7,151,681
App. No.
11/022,167
Granted
Dec 19, 2006
Kind
B2
Abstract

A multiple-sampling circuit is proposed for measuring a voltage signal and a discharge time of a transformer. Sampling signals are used for generating hold voltages by alternately sampling the reflected voltage from the transformer. A buffer amplifier generates a buffer voltage from the higher voltage of hold voltages. A sampling switch periodically conducts the buffer voltage to produce a voltage-feedback signal. The voltage-feedback signal is proportional to an output voltage of the switching circuit. A threshold signal added to the reflected voltage signal produces a level-shift reflected signal. A discharge-time signal is generated as the switching signal is disabled. The discharge-time signal is disabled once the level-shift signal is lower than the voltage-feedback signal. The pulse width of the discharge-time signal is therefore correlated to the discharge time of the transformer. The sampling signals are enabled to generate hold voltages only when the discharge-time signal is enabled.

Claims (15)

1. A multiple-sampling circuit applied in a switching controller for power supplies, connected to an auxiliary winding of a transformer, a PWM (pulse width modulation)-and-blanking unit, and an oscillating unit; said multiple-sampling circuit comprising:

a time-delay unit, connected to said PWM-and-blanking unit for receiving a switching signal, said time-delay unit generating a delay-time signal as said switching signal is disabled, said time-delay unit also generating an inverse switching signal via an inverter, wherein said switching signal is used to switch said transformer via a power switch;

a signal-generating unit, connected to said time-delay unit for receiving said delay-time signal and said inverse switching signal; said signal-generating unit also receiving a reflected voltage signal from said auxiliary winding of said transformer via a voltage divider; said signal-generating unit generating a discharge-time signal, a first sampling signal and a second sampling signal; and

a sampling unit, connected to said voltage divider, said oscillating unit, and said PWM-and-blanking unit for receiving said first sampling signal, said second sampling signal, said reflected voltage signal, a pulse signal generated by said oscillating unit, and a clear signal generated by said PWM-and-blanking unit; said sampling unit being controlled by said first sampling signal and said second sampling signal to sample said reflected voltage signal for generating a voltage-feedback signal.

2. The multiple-sampling circuit as claimed in claim 1 , said signal-generating unit comprising a threshold signal, wherein said threshold signal added to said reflected voltage signal to generate a level-shift reflected signal, wherein said discharge-time signal is generated as said switching signal is disabled, wherein said discharge-time signal is disabled as said level-shift reflected voltage signal is lower than said voltage-feedback signal, wherein a pulse width of said discharge-time signal is correlated to a discharge time of said transformer.

3. The multiple-sampling circuit as claimed in claim 1 , said signal-generating unit further comprising:

a sampling-pulse generator, generating a sampling-pulse signal for multiple-sampling operation;

a first signal generator, alternately generating said first sampling signal and said second sampling signal in response to said sampling-pulse signal during an enabled period of said discharge-time signal; wherein a delay time is inserted at the beginning of said discharge-time signal; wherein said first sampling signal and said second sampling signal are disabled during an period of said delay time; and

a second signal generator, for generating said discharge-time signal; wherein said discharge-time signal is enabled as said switching signal is disabled; wherein after said delay time, said discharge-time signal is disabled as said level-shift reflected signal is lower than said voltage-feedback signal; wherein said discharge-time signal can also be disabled as said switching signal is enabled.

4. The multiple-sampling circuit as claimed in claim 1 , said first sampling signal and said second sampling signal alternately controlling two switches to sample said reflected voltage signal for respectively obtaining a first hold voltage across a first capacitor and a second hold voltage across a second capacitor.

5. The multiple-sampling circuit as claimed in claim 1 , said sampling unit comprising a buffer amplifier connected to said first capacitor and said second capacitor for receiving said first hold voltage and said second hold voltage, wherein a buffer voltage is obtained from the higher voltage of said first hold voltage and said second hold voltage.

6. The multiple-sampling circuit as claimed in claim 3 , said sampling unit further comprising a sampling switch connected to said buffer amplifier, said sampling switch being cycle-by-cycle controlled by said pulse signal to conduct said buffer voltage to an output capacitor for generating said voltage-feedback signal.

7. The multiple-sampling circuit as claimed in claim 1 , wherein an end voltage is generated by multiple sampling said reflected voltage signal, said end voltage being measured before a secondary-side switching current falls to zero.

8. The multiple-sampling circuit as claimed in claim 1 , wherein said switching signal has a minimum on-time, wherein once said switching signal is enabled, said minimum on-time ensures a minimum discharge time for multiple sampling said reflected voltage signal.

9. The multiple-sampling circuit as claimed in claim 1 , wherein said switching signal has a minimum switching frequency to ensure a switching of said transformer for multiple sampling said reflected voltage signal.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 054090, FRAME 0617 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064081/0167 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
SECURITY INTEREST Recorded Oct 16, 2020
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION; ON SEMICONDUCTOR CONNECTIVITY SOLUTIONS, INC.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 054090/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 29, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 047619/0918 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2017
From: FAIRCHILD (TAIWAN) CORPORATION (FORMERLY SYSTEM GENERAL CORPORATION)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 042328/0318 →
CHANGE OF NAME Recorded Mar 22, 2017
From: SYSTEM GENERAL CORPORATION
To: FAIRCHILD (TAIWAN) CORPORATION
Reel/Frame 042068/0929 →