IP Library Granted Patent US 7,306,959
Granted Patent B2
US 7,306,959 · App. 11/022,364 · Granted Dec 11, 2007

Methods of fabricating integrated optoelectronic devices

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Quick Facts
Patent No.
US 7,306,959
App. No.
11/022,364
Granted
Dec 11, 2007
Kind
B2
Abstract

This disclosure concerns methods for fabrication of integrated high speed optoelectronic devices. In one example of such a method, a device region that includes a top surface and a bottom surface is formed on a top surface of a substrate. The device region may take the form of an optical emitter, such as a VCSEL, or a detector, such as a photodiode. Next, an isolation region is formed that is configured such that the device region is surrounded by the isolation region. A superstrate is then disposed on the top surface of the device region. Finally, a micro-optical device, such as a lens, is placed on a top surface of the superstrate.

Claims (44)

1. A method for fabricating an optoelectronic device, comprising:

forming, upon a top surface of a substrate, a device region that includes a top surface and a bottom surface;

forming an isolation region configured such that the device region is surrounded by the isolation region;

providing a superstrate on the top surface of the device region, the superstrate including a top surface; and

disposing a micro-optical device on the top surface of the superstrate.

2. The method as recited in claim 1 , wherein forming the device region comprises depositing a plurality of epitaxial layers.

3. The method as recited in claim 1 , wherein the device region is formed using MOCVD.

4. The method as recited in claim 1 , wherein the device region comprises one of: an optical emitter; or, an optical detector.

5. The method as recited in claim 1 , wherein the isolation region is formed by ion implantation of a portion of the device region and wherein formation of the isolation region includes definition of an active region.

6. The method as recited in claim 1 , wherein provision of a superstrate on the top surface of the device region comprises one of: formation of a superstrate on the top surface of the device region; or, attachment of a superstrate wafer to the top surface of the device region.

7. The method as recited in claim 1 , wherein the superstrate comprises a material that is optically transparent with regard to a wavelength associated with the device region.

8. The method as recited in claim 1 , wherein the micro-optical device comprises one of: a collimating lens; a focusing lens; and, a refractive lens.

9. The method as recited in claim 1 , further comprising bonding an integrated circuit to the bottom surface of the device region.

10. A method for fabricating an optoelectronic device, comprising:

forming, upon a top surface of a substrate, a device region that includes a top surface and a bottom surface;

forming, by ion implantation of a portion of the device region, a top isolation region configured such that the device region is surrounded by the top isolation region;

forming a p-type contact metal that extends across an unimplanted region of the device region and onto the surrounding top isolation region;

providing a superstrate on the top surface of the device region, the superstrate including a top surface;

removing the substrate;

forming, by ion implantation of a portion of the device region, a bottom isolation region configured and arranged to electrically isolate contacts of the device region;

forming an n-type contact metal that extends across an unimplanted region of the device region and onto the bottom isolation region;

forming a thru-epi via by etching an exposed surface of the device region through to the p-type contact metal;

forming a thru-epi metal such that the thru-epi metal traverses through the thru-epi via and contacts the p-type contact metal;

forming a first bond pad on the bottom isolation region, and forming a second bond pad on the n-type contact metal;

disposing a micro-optical device on the top surface of the superstrate; and

bonding an integrated circuit to the bottom surface of the device region.

11. The method as recited in claim 10 , wherein forming the device region comprises:

forming an n-type epilayer on the top surface of the substrate;

forming an active layer on the n-type epilayer; and

forming a p-type epilayer on the active layer.

12. The method as recited in claim 11 , wherein formation of the top isolation region is performed by hydrogen implantation of the p-type epilayer; and, a portion of the n-type epilayer.

13. The method as recited in claim 10 , wherein the p-contact metal is formed using E-beam deposition.

14. The method as recited in claim 10 , further comprising formation of emitter/illumination window in the p-contact metal.

15. The method as recited in claim 10 , wherein the superstrate is adhered to the device region with an optically transparent adhesive.

16. The method as recited in claim 10 , wherein the n-contact metal is formed using E-beam deposition.

17. The method as recited in claim 10 , wherein the thru-epi via is formed by RIE.

18. The method as recited in claim 10 , wherein forming a thru-epi metal comprises electro-plating gold.

19. The method as recited in claim 10 , wherein the bond pads are bump bonded to matching pads of the integrated circuit.

20. A method for fabricating an optoelectronic device, comprising:

forming, upon a top surface of a substrate, a device region;

forming an isolation region configured such that the device region is surrounded by the isolation region;

forming a contact layer on the device region;

providing a superstrate on a top surface of the device region and the contact layer; and

disposing a micro-optical device on a top surface of the superstrate.

Assignments (3)
PATENT RELEASE AND REASSIGNMENT Recorded Jul 5, 2022
From: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
To: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
Reel/Frame 060574/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2020
From: FINISAR CORPORATION
To: II-VI DELAWARE, INC.
Reel/Frame 052286/0001 →
NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Recorded Sep 25, 2019
From: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 050484/0204 →