Clock control method and circuit
View Patent ↗A clock control circuit for reducing jitter has at least one averaging circuit for generating, and outputting from an output terminal, a signal having a time difference obtained by internally dividing a time difference between first and second signals input respectively from first and second input terminals. First and second clock signals are supplied respectively to the first and second input terminals of the timing averaging circuit, and a clock in which a time difference between pulses of the first and second clock signals is averaged is generated.
1. A timing circuit comprising:
frequency dividing means which divides a frequency of a timing signal and outputs a first signal having a first phase and a second signal having a second phase;
parallel circuits which each receive the first and second signal and generate an output signal at a time referenced from a transition of the earlier occurring signal of the first and second signals, and
wherein the output signal generation time is determined by a time difference between a low-to-high transition of the first signal and a low-to-high transition of the second signal or between a high-to-low transition of the first signal and a high-to-low transition of the second signal; and
means for combining the output signals from the parallel circuits to recover the frequency of the timing signal.
2. The timing circuit of claim 1 wherein the parallel circuits comprise a stage and a plurality of stages are serially connected.
3. A timing circuit comprising:
a frequency dividing circuit which divides a frequency of a timing signal and outputs a first signal having a first phase and a second signal having a second phase;
parallel circuits which each receive the first and second signal and generate an output signal at a time referenced from a transition of the earlier occurring signal of the first and second signals, and
wherein the output signal generation time is determined by a time difference between a low-to-high transition of the first signal and a low-to-high transition of the second signal or between a high-to-low transition of the first signal and a high-to-low transition of the second signal; and
a multiplexing circuit which combines the output signals from the parallel circuits to recover the frequency of the timing signal.
4. The timing circuit of claim 3 wherein the parallel circuits comprise a stage and a plurality of stages are connected in series.