Liquid crystal display device with data and gate link lines having holes for resistance compensation for providing constant current flow therebetween
View Patent ↗A liquid crystal display (LCD) device compensates the resistance value for differing line lengths by forming resistance compensation holes in gate and data link lines, and obtains a constant current flowing in the gate and data lines, and includes an active region including a plurality of gate and data lines crossing each other to define a plurality of pixel regions, and a thin film transistor and a pixel electrode formed in each pixel region; gate link lines and a data link lines respectively extending from the gate lines and the data lines in the periphery of the active region; first resistance compensation holes in the gate link lines to compensate a resistance value of the gate link lines having different lengths; second resistance compensation holes in the data link lines to compensate a resistance value of the data link lines having different lengths; a gate pad at an end of the gate link lines; and a data pad at an end of the data link lines.
1. A liquid crystal display (LCD) device comprising:
an active region including a plurality of gate lines and data lines crossing each other;
gate pads and data pads;
gate link lines between the gate lines and the gate pads;
data link lines between the data lines and the data pads;
a first resistance compensation structure including at least one recess or hole in at least one of the gate link lines to compensate a resistance value of the gate link lines; and
a second resistance compensation structure including at least one recess or hole in at least one of the data link lines to compensate a resistance value of the data link lines, wherein the first resistance compensation structure is formed at the same time the gate link lines are patterned and the second resistance compensation structure is formed at the same time the data link lines are patterned,
wherein the number of first resistance compensation structures in the gate link lines increases with decreasing lengths of the gate link lines, and the number of second resistance compensation structures in the data link lines increases with decreasing lengths of the data link lines, and
wherein the longest gate link line does not include the first resistance compensation structure, and the longest data link line does not include the second resistance compensation structure.
2. The liquid crystal display device according to claim 1 , wherein a constant current is transmitted to the gate lines through the gate link lines having the first resistance compensation structure.
3. The liquid crystal display device according to claim 1 , wherein a constant current is transmitted to the data lines through the data link lines having the second resistance compensation structure.
4. A method for producing a liquid crystal display device, comprising the steps of:
forming an active region including a plurality of gate lines and data lines crossing each other;
forming gate link lines and data link lines extending from the gate lines and the data lines, respectively;
forming gate pads and data pads at ends of the gate and data link lines; and
forming a first resistance compensation structure including at least one recess or hole in at least one of the gate link lines to compensate a resistance value of the gate link lines, and/or forming a second resistance compensation structure including at least one recess or hole in at least one of the data link lines to compensate a resistance value of the data link lines,
wherein the first resistance compensation structure is formed at the same time the gate link lines are patterned and the second resistance compensation structure is formed at the same time the data link lines are patterned,
wherein the number of the formed first resistance compensation structures in the gate link lines increases with decreasing lengths of the gate link lines and/or the gate lines, and the number of the formed second resistance compensation structures in the data link lines increases with decreasing lengths of the data link lines and/or the data lines, and
wherein the first resistance compensation structure is not formed in the longest gate link line, and the second resistance compensation structure is not formed in the longest data link line.
5. The method according to claim 4 , wherein the first resistance compensation structure is formed such that a constant current is transmitted to the gate lines through the gate link lines having the first resistance compensation structure.
6. The method according to claim 4 , wherein the second resistance compensation structure is formed such that a constant current is transmitted to the data lines through the data link lines having the second resistance compensation structure.