Method for fabricating transistor of semiconductor device

1. A method for fabricating a transistor of a semiconductor device comprising:

forming an STI structure and a well region in a silicon substrate;

forming a first dummy gate electrode including spacers and a first gate oxide layer on the well region;

forming source and drain regions around the first dummy gate electrode by using the first dummy gate electrode and the spacers as an ion implantation mask, and performing a thermal treatment;

removing the first dummy gate electrode and the first gate oxide layer;

forming a second dummy gate electrode and a second gate oxide layer;

forming a thin nitride layer and a PMD on the silicon substrate including the second dummy gate electrode;

performing a CMP process for the thin nitride layer and the PMD until the top of the spacers is exposed;

removing the second dummy gate electrode and the second gate oxide layer;

forming a third gate oxide layer and polysilicon for a gate electrode;

performing another CMP process until the top of the spacers is exposed; and

etching the upper portion of the gate electrode,

wherein forming a first dummy gate electrode including the spacers and a first gate oxide layer on the well region comprises:

forming a first gate oxide layer on the silicon substrate including the well region; depositing polysilicon for first dummy gate electrode;

patterning the first gate oxide layer and the polysilicon into a first dummy gate;

forming a LDD structure around the first dummy gate electrode;

depositing a nitride layer on the entire surface of the substrate; and

forming the spacers on the lateral faces of the first dummy gate electrode by patterning the nitride layer.

2. A method as defined by claim 1 , further comprising forming a silicide layer on the top of the gate electrode and the source and drain regions after the upper portion of the gate electrode is etched.

3. A method as defined by claim 2 , wherein the suicide layer is made of Co or Ni.

4. A method as defined by claim 1 , wherein the thermal treatment is performed at about 800° C.

5. A method as defined by claim 1 , wherein the second gate oxide layer is formed by a plasma oxidation process.

6. A method as defined by claim 1 , wherein the third gate oxide layer is made of a material having a high dielectric constant.

7. A method as defined by claim 1 , wherein the gate electrode is additionally wet-etched by 300 Å to 500 Å.

8. A method as defined by claim 1 , wherein the thermal treatment is an RTA.