Layered crossbar for interconnection of multiple processors and shared memories

1. An apparatus comprising:

a first processor switch comprising a plurality of processors and a processor crossbar, each processor coupled to the processor crossbar; and

a plurality of memory switches, each comprising a plurality of memory controllers and a memory crossbar, each memory controller in a memory switch coupling to the memory crossbar of the memory switch, and each memory crossbar in each of the memory switches coupling to the processor crossbar,

wherein a first integrated circuit comprises the processor switch and a second integrated circuit comprises at least one of the memory switches.

2. The apparatus of claim 1 further comprising:

a second processor switch comprising a plurality of processors and a processor crossbar, each processor coupling to the processor crossbar,

wherein each memory crossbar in each of the memory switches is coupled to the processor crossbars of the first and second processor switches.

3. The apparatus of claim 1 further comprising:

a plurality of memory tracks each having a plurality of shared memory banks; and

a plurality memory buses, each coupling a memory controller to a memory track,

wherein a memory switch is fabricated on a different integrated circuit than a memory track.

4. The apparatus of claim 3 wherein the memory tracks further comprise at least one SDRAM, wherein the SDRAM includes at least one memory bank.

5. A method comprising:

implementing a first processor switch comprising a plurality of processors and a processor crossbar, each processor coupled to the processor crossbar;

implementing a plurality of memory switches, each comprising a plurality of memory controllers and a memory crossbar, each memory controller in a memory switch coupling to the memory crossbar of the memory switch, and each memory crossbar in each of the memory switches coupling to the processor crossbar; and

connecting the processor crossbar with each memory crossbar of each memory switch.

6. An apparatus comprising:

a plurality of processor switches, wherein each processor switch comprises:

a plurality of processors; and

a processor crossbar,

wherein each processor in a processor switch is coupled to the processor crossbar of the processor switch;

a first plurality of memory switches, each comprising a plurality of memory controllers and a memory crossbar, each memory controller in a memory switch coupling to the memory crossbar of the memory switch; and

a first-level intermediate switch comprising a switch crossbar, wherein the switch crossbar is coupled to the processor crossbars and the memory crossbars,

wherein a first integrated circuit comprises the processor switches and a second integrated circuit comprises the memory switches.

7. The apparatus of claim 6 wherein a third integrated circuit comprises the first-level intermediate switch.

8. The apparatus of claim 7 wherein the processor switch is separate from the first-level intermediate switch.

9. The apparatus of claim 6 wherein the first integrated circuit comprises the first-level intermediate switch.

10. The apparatus of claim 9 wherein the memory switch is separate from the first-level intermediate switch.

11. The apparatus of claim 6 wherein the second integrated circuit comprises the first-level intermediate switch.

12. The apparatus of claim 6 further comprising:

a second plurality of memory switches, each comprising a plurality of memory controllers and a memory crossbar, each memory controller in a memory switch coupling to the memory crossbar of the memory switch; and

a plurality of second-level intermediate switches, each comprising a switch crossbar,

wherein the first plurality of memory switches are coupled to the first-level intermediate switch through a first second-level intermediate switch, and

the second plurality of memory switches are coupled to a second second-level intermediate switch, and

the second second-level intermediate switch is coupled to the first-level intermediate switch.

13. The apparatus of claim 6 wherein a processor group further comprises:

a plurality of clients;

a plurality of caches;

a plurality of reorder units; and

a client funnel, wherein the client funnel is coupled to the caches and the reorder units,

wherein the clients manage memory requests from processes executing within a processor.

14. The apparatus of claim 6 wherein the processor crossbar further comprises:

an input port comprising:

a client interface;

a queue which further comprises a queue controller and at least one request station;

an arbiter; and

a multiplexer,

wherein the processor crossbar passes memory transactions from a processor to a switch crossbar.

15. The apparatus of claim 14 wherein the input port further comprises:

a segment interface; and

a tag generator,

wherein the input port is located within a switch crossbar.

16. The apparatus of claim 15 wherein the tag generator further comprises:

a counter; and

a memory,

wherein the memory is a two-port memory that is one bit wide.

17. The apparatus of claim 16 further comprising a priority encoder that implements a binary truth table.

18. The apparatus of claim 14 wherein the request station further comprises:

a forward register;

a reverse register; and

a delay buffer.