IP Library Granted Patent US 7,118,965
Granted Patent B2
US 7,118,965 · App. 11/024,194 · Granted Oct 10, 2006

Methods of fabricating nonvolatile memory device

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Quick Facts
Patent No.
US 7,118,965
App. No.
11/024,194
Granted
Oct 10, 2006
Kind
B2
Abstract

A fabricating method of a nonvolatile memory device is disclosed. A disclosed method comprises: implanting ions into an active region of a semiconductor substrate to form a well of a low voltage transistor and adjust its threshold voltage; implanting ions into an active region of the semiconductor substrate to form a well of a high voltage transistor and adjust its threshold voltage, thereby forming a conductive region; depositing an ONO layer on the semiconductor substrate; patterning and etching the ONO layer to form an ONO structure; and forming a gate oxide layer on the semiconductor substrate.

Claims (12)

1. A method of fabricating a nonvolatile memory device comprising:

forming a nonvolatile memory structure, including:

implanting first ions into an active region of a semiconductor substrate to form a first well and to adjust a threshold voltage of a low voltage n-type MOS transistor and a threshold voltage of a high voltage n-type MOS transistor;

implanting second ions into active region of the semiconductor substrate to form a second well and to adjust a threshold voltage of a high voltage p-type MOS transistor and a threshold voltage of a low voltage p-type MOS transistor, thereby forming a conductive region;

depositing an ONO layer on the semiconductor substrate;

patterning and etching the ONO layer to form an ONO structure;

after forming the ONO structure, forming a first gate oxide layer on the semiconductor substrate;

removing the first gate oxide layer existing where the low voltage n-type MOS transistor and the low voltage p-type MOS transistor are to be formed; and

forming a second gate oxide layer for the low voltage n-type MOS transistor and the low voltage p-type MOS transistor; and

after forming the nonvolatile memory structure, forming a logic circuit.

2. A method as defined by claim 1 , wherein the ONO structure is formed by patterning and wet etching the ONO layer.

3. A method as defined by claim 1 , wherein the formation of the gate oxide layer includes a thermal oxidation process.

Assignments (2)
CHANGE OF NAME Recorded Jul 13, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 018099/0256 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 29, 2004
From: LEE, SANG BUM; JUNG, JIN HYO; KWON, SUNG WOO
To: DONGBUANUM SEMICONDUCTOR INC.
Reel/Frame 016139/0574 →