Multi-concentric pad arrangements for integrated circuit pads
View Patent ↗Multi-concentric pad (MCP) arrangements provide for increased pad densities on integrated circuits. The multi-concentric pad (MCP) configuration includes a first set of input output (IO) pads and a second set of IO pads, both disposed on an integrated circuit die. Each IO pad in said first set and said second set of IO pads includes a bond pad for receiving a bond wire connection, and an IO circuit coupled to the bond pad. The IO circuits provide an interface between a signal received at the corresponding bond pad and a core circuit disposed on said IC die. The first set of IO pads are arranged closer to the perimeter of the IC die than the second set of IO pads. Furthermore, the second set of IO pads are arranged so that each IO circuit in the second set of IO pads is closer to the center of the IC die than a corresponding IO circuit in the first set of IO pads.
1. An integrated circuit (IC) die comprising:
a first set of input/output (I/O) circuits; and
a second set of I/O circuits;
a first set of bond pads coupled to corresponding I/O circuits of said first set of I/O circuits; and
a second set of bond pads coupled to corresponding I/O circuits of said second set of I/O circuits;
wherein said first set of I/O circuits is placed proximate a first edge portion of said IC die and said second set of I/O circuits is placed farther away from said first edge portion than said first set of I/O circuits.
2. The IC die of claim 1 , wherein said first set of bond pads and said second set of bond pads are in an inline arrangement.
3. The IC die of claim 1 , wherein said first set of bond pads are in a staggered arrangement and said second set of bond pads are in a staggered arrangement.
4. The IC die of claim 1 , wherein said first set of bond pads are in a staggered arrangement and said second set of bond pads are in an inline arrangement.
5. The IC die of claim 1 , wherein said first set of bond pads are in an inline arrangement and said second set of bond pads are in a staggered arrangement.
6. The IC die of claim 1 , wherein, in a direction parallel to said first edge portion, said first set of I/O circuits and said second set of I/O circuits are not aligned.
7. The IC die of claim 1 , wherein said first and second sets of I/O circuits are coupled via a mesh interconnect.
8. The IC die of claim 1 , wherein said mesh interconnect provides electrostatic discharge protection.
9. The IC die of claim 7 , wherein electrical signals can be transmitted to and from said first and second sets of I/O circuits via said mesh interconnect.
10. The IC die of claim 1 , wherein said first and second I/O circuits are coupled to an IC package via at least one bond wire.
11. The IC die of claim 1 , wherein adjacent I/O circuits and their corresponding bond pads are configured to allow at least one wire to pass between said adjacent I/O circuits and their corresponding bond pads.
12. The IC die of claim 11 , wherein said adjacent I/O circuits and their corresponding bond pads are undersized to allow passage of said at least one wire.
13. The IC die of claim 1 , wherein said first and second sets of bond pads interface an external circuit to said IC die and said first and second set of I/O circuits interface to core circuitry disposed on said IC die.
14. The IC die of claim 1 , wherein said IC die is configured with a flip-chip redistribution layer.
15. The IC die of claim 1 , wherein said first set of I/O circuits and said second set of I/O circuits receive and transmit distinct signals.
16. The IC die of claim 1 , wherein each bond pad in said first and second set of bond pads is coupled to a bond wire connection in a direction away from said first edge portion to enable connections with circuitry exterior to said IC die.