Methods of fabricating non-volatile memory devices
View Patent ↗Methods of fabricating non-volatile memory devices are disclosed. The resulting non-volatile memory devices include an additional protection film is formed on a control gate pattern to enable the control gate pattern to have a regular and smooth profile regardless of an etching process progressed intensively for removing an active cell isolation film from an active cell isolation trench by using the control gate pattern as a mask, so that the control gate pattern can avoid influence from the impurity even if an impurity injection process is progressed for forming a source diffusion layer, later.
1. A method for fabricating a non-volatile memory device, comprising:
preparing a semiconductor substrate having a trench filled with an isolation film;
forming a tunnel oxide film, a first conductive layer, an Oxide-Nitride-Oxide (ONO) layer, and a second conductive layer on the semiconductor substrate in succession;
forming a protection layer on the second conductive layer wherein forming the protection layer comprises a silicide process;
etching the first conductive layer, the ONO layer, the second conductive layer, and the protection layer, to form gate stacks on opposed sides of the isolation film, the gate stacks exposing a portion of the isolation film between the opposed sides, each gate stack comprising a floating gate pattern, an ONO pattern, a control gate pattern, and a protection pattern, and having a first portion over the isolation film in the trench and a second portion over the tunnel oxide film on the substrate;
forming a photoresist pattern for a self aligned source (SAS) over the semiconductor substrate in such a way that a part of the silicide top surface of the protection pattern and the exposed portion of the isolation film remain uncovered therewith;
etching the exposed portion of the isolation film using the photoresist pattern and the part of the protection pattern as an etching mask; and
injecting impurity ions into a bottom of the trench, to form a source diffusion layer.
2. A method as defined by claim 1 , wherein the silicide process comprises:
depositing a metal layer on the second conductive layer, and
performing a heat treatment process, to make the metal layer react with the second conductive layer, to convert the metal layer into a silicide layer.
3. A method as defined by claim 2 , wherein the metal layer comprises a Ti thin film layer or a Co thin film layer.
4. A method as defined by claim 1 , wherein the protection layer has a thickness of about 150 Å to about 250 Å.
5. A method as defined by claim 1 , wherein the tunnel oxide film has a thickness of about 100 Å to about 200 Å.
6. A method as defined by claim 1 , wherein the first conductive layer has a thickness of about 1000 Å to about 1500 Å.
7. A method as defined by claim 1 , wherein the second conductive layer has a thickness of about 1000 Å to about 2000 Å.
8. A method as defined by claim 1 , wherein the first conductive layer comprises an undoped polysilicon layer.
9. A method as defined by claim 1 , wherein forming the first conductive layer comprises a CVD process.
10. A method as defined by claim 1 , further comprising forming the trench and isolation film by a STI process.
11. A method as defined by claim 1 , wherein forming the tunnel oxide film comprises a thermal oxidation process.
12. A method as defined by claim 1 , wherein forming the tunnel oxide film comprises a CVD process.
13. A method as defined by claim 1 , wherein forming the ONO layer comprises a series of CVD processes.
14. A method as defined by claim 1 , wherein the second conductive layer comprises undoped polysilicon.
15. A method as defined by claim 1 , wherein etching the first conductive layer, the ONO layer, the second conductive layer, and the protection layer comprises a photo-etching process.
16. A method as defined by claim 2 , wherein depositing the metal layer comprises a sputtering process.
17. A method as defined by claim 1 , wherein etching the exposed portion of the isolation film leaves a second portion of the isolation film along sidewalls of the trench.
18. A method as defined by claim 1 , wherein the protection pattern reduces art amount of the impurity ions injected into the second conductive layer.
19. A method as defined by claim 1 , wherein, after the gate stacks are formed, a cross-section of the device includes the first and second portions of the gate stacks and the bottom of the trench between the gate stacks.