Method of forming reduced short channel field effect transistor
View Patent ↗A method for manufacturing a semiconductor device capable of reducing a short channel effect, whereby the semiconductor device includes a pair of impurity regions for a source and a drain formed on a semiconductor substrate, a gate having a gate electrode used to control a drain current, side walls formed on both sides of the gate electrode, and a pair of electrode members formed on both sides of the semiconductor substrate and in contact with the side walls. First impurity regions are formed by thermal diffusion of impurities from each of the electrode members, and second impurity regions each having thickness smaller than the first impurity region and extending below the gate electrode are formed by thermal diffusion of impurities from the side walls.
1. A method for manufacturing a semiconductor device, comprising:
forming a silicon layer on a semiconductor substrate;
forming a metallic layer on the silicon layer;
implanting an impurity into the metallic layer;
etching the silicon layer and the implanted metallic layer to provide a pair of spaced apart electrode members;
performing a first heat treatment to change the silicon layer to a metallic silicide layer;
forming an insulating layer on the electrode members and on portions of the semiconductor substrate exposed between the electrode members;
implanting the impurity into the insulating layer;
removing unwanted portions of the implanted insulating layer to form side walls on the electrode members that face each other with intervals therebetween;
forming a gate electrode on the semiconductor substrate between the side walls; and
thermally diffusing the impurity simultaneously from each of the electrode members and from the side walls to respectively form first impurity regions under the electrode members and second impurity regions under the side walls,
wherein said forming a gate electrode is performed after formation of the electrode members and the side walls.
2. The method for manufacturing a semiconductor device of claim 1 , wherein thickness of the second impurity regions is smaller than thickness of the first impurity regions.