Optical receiver
View Patent ↗A receiver for a differentially phase shift keying formatted optical signal, such as an RZ-DPSK formatted optical signal. Dither control loops are provided for controlling path length in a demodulator and/or for controlling the center wavelength of an optical band pass filter. A feedback loop is provided for controlling the gain of a pre-amplifier, and a method of protecting against optical transients by disabling a pre-amplifier is also provided. A preset delay may be provided to compensate for the differential delay in paths associated with the demodulator arms. When the signal is an RZ-DPSK modulated signal, a clock for retiming data from the optical signal may be derived from a signal on the data path.
1. An apparatus comprising:
a demodulator for demodulating an optical input signal having data modulated thereon according to a DPSK modulation format, said demodulator being configured to split said optical input signal onto first and second arms and provide first and second optical outputs;
first and second photodetectors, said first photodetector being configured for providing a first electrical output in response to said first optical output being imparted thereon, said second photodetector being configured for providing a second electrical output in response to said second optical output being imparted thereon;
an integrated clock and data recovery circuit coupled to first and second electrical outputs, said integrated clock and data recovery circuit being configured to provide a signal level output representative of a signal level of at least one of said first and second electrical outputs;
a first dither circuit for establishing a demodulator dither signal;
a controller configured for providing a demodulator setting signal in response to said signal level output; and
a combiner for combining said demodulator dither signal and said demodulator setting signal as a demodulator control signal for controlling and dithering an optical path length of one of said first and second arms.
2. An apparatus according to claim 1 , wherein said controller is configured to control said optical path length to achieve a phase relationship of kπ, where k is in an integer value, between light traveling on said one of said first and second arms compared to light traveling on the other of said first and second arms.
3. An apparatus according to claim 1 , said apparatus further comprising an error detection circuit for providing an error signal in response to said signal level output and a demodulator dither reference signal, and wherein said demodulator setting signal is provided by said controller in response to said demodulator error signal.
4. An apparatus according to claim 3 , wherein said controller is configured to adjust said demodulator setting signal to minimize said demodulator error signal.
5. An apparatus according to claim 3 , wherein said error detection circuit comprises a synchronous phase detector.
6. An apparatus according to claim 3 , said apparatus comprising a second dither circuit for establishing said demodulator dither reference signal.
7. An apparatus according to claim 6 , wherein said demodulator dither signal and said demodulator dither reference signal are established by said first and second dither circuits, respectively, in response to a common clock input.
8. An apparatus according to claim 6 , wherein said second dither circuit is configured for imparting a selectable relative phase difference between said demodulator dither signal and said demodulator dither reference signal.
9. An apparatus according to claim 6 , wherein said first and second dither circuits comprise separate direct digital synthesizers.
10. An apparatus according to claim 1 , said apparatus further comprising an amplifier configured to receive said demodulator dither signal and establish an amplitude of said demodulator dither signal in response to an amplitude of said demodulator setting signal.
11. An apparatus according to claim 1 , wherein said DPSK format is a RZ-DPSK format.
12. An apparatus according to claim 1 , wherein said demodulator comprises a Mach-Zehnder demodulator.
13. An apparatus according to claim 1 , wherein said integrated clock and data recovery circuit is configured to provide first and second ones of said signal level outputs, and wherein said controller is configured for providing said demodulator setting signal in response to said first and second signal level outputs.
14. A method of stabilizing a demodulator configured to split a DPSK formatted optical input signal onto first and second arms and provide first and second optical outputs, said method comprising:
coupling an output of said demodulator to an integrated clock and data recovery circuit, said integrated clock and data recovery circuit being configured to provide a signal level output representative of a signal level of at least one of said first and second outputs; and
providing a demodulator dither signal;
providing a demodulator setting signal in response to said signal level output; and
combining said demodulator dither signal with said demodulator setting signal as a demodulator control signal for controlling and dithering an optical path length of one of said first and second arms.
15. A method according to claim 14 , said demodulator setting signal is configured to establish a phase relationship of kπ, where k is in an integer value, between light traveling on said one of said first and second arms compared to light traveling on the other of said first and second arms.
16. A method according to claim 14 , said method further comprising generating a demodulator error signal in response to said signal level output and a demodulator dither reference signal, and wherein said demodulator setting signal is provided in response to said demodulator error signal.
17. A method according to claim 16 , said method further comprising providing a first dither circuit for establishing said demodulator dither signal and providing a second dither circuit for establishing said demodulator dither reference signal.
18. A method according to claim 17 , wherein said demodulator dither signal and said demodulator dither reference signal are synthesized by said first and second dither circuits, respectively, in response to a common clock input.
19. A method according to claim 16 , said method further comprising imparting a phase difference between said demodulator dither signal and said demodulator dither reference signal.
20. A method according to claim 14 , said method further establishing an amplitude of said demodulator dither signal in response to an amplitude of said demodulator setting signal.
21. A method according to claim 14 , wherein said integrated clock and data recovery circuit is configured to provide first and second ones of said signal level outputs, and wherein said controller is configured for providing said demodulator setting signal in response to said first and second signal level outputs.
22. An apparatus comprising:
a demodulator for demodulating an optical input signal, said demodulator being configured to split said optical input signal onto first and second arms and provide first and second optical outputs;
a first dither circuit for establishing a demodulator dither signal;
a controller configured for providing a demodulator setting signal;
a combiner for combining said demodulator dither signal and said demodulator setting signal as a demodulator control signal for controlling and dithering an optical path length of one of said first and second arms;
a second dither circuit for establishing a demodulator dither reference signal; and
an error detection circuit for providing an error signal in response to a feedback signal representative of a signal level of at least one of said first and second optical outputs and said demodulator dither reference signal, said controller being configured for providing said demodulator setting signal in response to said demodulator error signal.
23. An apparatus according to claim 22 , wherein said demodulator dither signal and said demodulator dither reference signal are established by said first and second dither circuits, respectively, in response to a common clock input.
24. An apparatus according to claim 22 , wherein said second dither circuit is configured for imparting a selectable phase difference between said demodulator dither signal and said demodulator dither reference signal.
25. An apparatus according to claim 22 , wherein said first and second dither circuits comprise separate direct digital synthesizers.
26. An apparatus according to claim 22 , said apparatus further comprising an amplifier configured to receive said demodulator dither signal and establish an amplitude of said demodulator dither signal in response to an amplitude of said demodulator setting signal.
27. An apparatus according to claim 22 , wherein said error detection circuit comprises a synchronous phase detector.
28. An apparatus according to claim 22 , wherein said demodulator comprises a Mach-Zehnder demodulator.
29. A method of stabilizing an demodulator configured to split an optical input signal onto first and second arms and provide first and second optical outputs, said method comprising:
providing a first dither circuit for establishing a demodulator dither signal;
controlling and dithering an optical path length of one of said first and second arms in response to said demodulator dither signal and a demodulator setting signal;
providing a second dither circuit for establishing a demodulator dither reference signal; and
generating said demodulator setting signal in response to a feedback signal representative of a signal level of at least one of said first and second optical outputs and said demodulator dither reference signal.
30. A method according to claim 29 , said method further comprising imparting a phase difference between said demodulator dither signal and said demodulator dither reference signal.
31. A method according to claim 29 , wherein said first and second dither circuits comprise separate direct digital synthesizers.
32. A method according to claim 29 , said method further establishing an amplitude of said demodulator dither signal in response to an amplitude of said demodulator setting signal.
33. A method according to claim 29 , wherein said demodulator comprises a Mach-Zehnder demodulator.