System and method for dynamically accessing memory while under normal functional operating conditions
View Patent ↗A system and method for dynamically accessing memory under normal operating conditions without interrupting computer system clocks that are otherwise executing. At least a memory access mode and a memory address(es) are scanned into a control scan chain from a maintenance system. When the scan is complete, the information is collectively transferred to an access register bank. Based on the control signals, a selection multiplexer selects the information from the control scan chain provided by the maintenance system as opposed to standard signals generated by the computer system. Memory control input signals are generated in response to a clock trigger signal, and the read or write data transfer is initiated.
1. A method for use in dynamically transferring data between a maintenance processing system and a system memory of a computing system during normal functional operation of the computing system, the method comprising:
serially scanning at least a memory access mode and a system memory address into a control scan chain;
collectively stepping the memory access mode and the system memory address from the control scan chain into an access register bank in response to a first trigger signal; and
generating system memory control inputs in response to a second trigger signal and initiating the dynamic transfer of the data between the system memory and the maintenance processing system in response thereto.
2. The method of claim 1 , wherein the memory access mode is distinguishable from a normal functional mode by which the computing system engages in the normal functional operation.
3. The method of claim 1 , wherein the memory access mode comprises a memory write mode indicating the dynamic transfer of the data involves writing the data to the system memory.
4. The method of claim 3 , further comprising serially scanning the data into a data scan register, and wherein collectively stepping comprises collectively stepping the memory access mode and the system memory address from the control scan chain into an access register bank, and stepping the data from the data scan register to the access register bank, in response to the first trigger signal.
5. The method of claim 4 , further comprising transferring the data from the access register bank to the system memory in response to the second trigger signal and according to the system memory control inputs.
6. The method of claim 1 , wherein the memory access mode comprises a memory read mode indicating the dynamic transfer of the data involves reading the data from the system memory.
7. The method of claim 6 , further comprising transferring the data from the system memory into a data scan register, and serially scanning out the data from the data scan register.
8. The method of claim 1 , further comprising providing the first trigger signal in response to completion of the serial scanning into the control scan chain.
9. The method of claim 8 , further comprising monitoring for the completion of the serial scanning into the control scan chain by the maintenance processing system, and providing the first trigger signal in response thereto.
10. A memory access system for facilitating dynamic access of memory by way of a maintenance processing system during standard operation of a computing system which utilizes the memory, comprising:
a control register bank coupled to receive scanned address and control signals, wherein the control signals include at least a maintenance mode control signal indicative of a memory access operation via the maintenance processing system;
an access register bank;
a step multiplexer coupled to the control register bank to transfer the scanned address and control signals from the control register bank to the access register bank in response to completion of receipt of the scanned address and control signals; and
a select multiplexer coupled to the access register bank to, in response to a clock trigger signal, select the scanned address and control signals as opposed to standard operational address and control signals produced by the computing system, wherein the scanned address and control signals specify data locations and access mode at the memory.
11. The memory access system as in claim 10 , wherein the control register bank comprises a plurality of serially scannable registers coupled in series to receive the scanned address and control signals.
12. The memory access system as in claim 10 , further comprising a data register coupled to receive data to be written from the maintenance processing system to the memory.
13. The memory access system as in claim 12 , wherein the data register comprises a serially scannable data register coupled to the maintenance processing system to serially receive the data to be written.
14. The memory access system as in claim 12 , wherein the step multiplexer is further coupled to the data register to transfer the data from the data register to the access register bank in response to completion of receipt of the scanned address, the control signals, and the data.
15. The memory access system as in claim 14 , wherein the control signals comprise a write mode signal, and wherein the select multiplexer is coupled to the access register bank to further select the data originating from the maintenance processing system as opposed to data produced by the computing system, in response to the maintenance mode control signal and the write mode signal.
16. The memory access system as in claim 15 , wherein the memory comprises a read/write control input to receive the write mode signal, and to store the data originating from the maintenance processing system in response to receipt of the write mode signal.
17. The memory access system as in claim 16 , further comprising an address incrementor coupled to the access register bank to receive the scanned address and to increment the scanned address for each subsequent data block to be written to the memory.
18. The memory access system as in claim 10 , wherein the scanned control signals comprise a read mode signal specifying a read memory mode as the access mode at the memory.
19. The memory access system as in claim 18 , further comprising a data register coupled to receive data read from the memory.
20. The memory access system as in claim 19 , further comprising an address incrementor coupled to the access register bank to receive the scanned address and to increment the scanned address for each subsequent data block to be read from the memory.
21. The memory access system as in claim 19 , wherein the data register comprises a serially scannable data register coupled to the maintenance processing system to serially transfer the data to the maintenance processing system.
22. A system for dynamically accessing memory operating in a computing system, the system comprising:
a maintenance processing system having a processor configured to generate first and second trigger signals, and to generate serial scan data including at least one memory address of the memory and control signals including a maintenance mode control signal indicative of a memory access operation via the maintenance processing system; and
a block mode wrapper coupled between the maintenance processing system and the memory, the block mode wrapper comprising:
a control register bank coupled to receive the serial scan data;
an access register bank;
a step multiplexer coupled to the control register bank to transfer the serial scan data from the control register bank to the access register bank in response to the first trigger signal; and
a select multiplexer coupled to the access register bank to, in response to the maintenance mode control signal and the second trigger signal, select the memory address and control signals from the maintenance processing system as opposed to standard operational address and control signals produced by the computing system, wherein the scanned address and control signals specify data locations and access mode at the memory.
23. The system as in claim 22 , wherein the processor of the maintenance processing system is configured to transmit the first trigger signal upon completion of scanning the serial scan data into the control register bank.
24. The system as in claim 22 , further comprising a serially scannable data register coupled to receive data to be written from the maintenance processing system to the memory, and wherein the processor of the maintenance processing system is configured to transmit the first trigger signal upon completion of scanning both the serial scan data into the control register bank and the data into the serially scannable data register.
25. The system as in claim 22 , further comprising a serially scannable data register coupled to receive data read from the memory.
26. The system as in claim 22 , wherein the memory comprises one of a single-port memory or a multiple-port memory.
27. An apparatus for use in dynamically transferring data between a maintenance processing system and a system memory of a computing system during normal functional operation of the computing system, the apparatus comprising:
register means for dynamically receiving serial scan data including at least a memory access mode and a memory address;
an access register bank;
means for collectively stepping the memory access mode and the memory address from the register means to the access register bank in response to the serial scan data being received at the register means; and
means for generating memory control input signals in response to a second trigger signal, and for initiating the dynamic transfer of the data between the memory and the maintenance processing system in response thereto.