Method and circuit configuration for synchronous resetting of a multiple clock domain circuit
View Patent ↗A method and circuit configuration for synchronous resetting of an multiple clock domain circuit such as an Application Specific Integrated Circuit (ASIC) combine an asynchronous reset signal with a functional signal using a clocked reset tree of synchronous logic elements.
1. A method for synchronous resetting of a multiple clock domain integrated circuit, comprising:
forming a clocked reset tree comprising a first synchronous logic element and at least one branched synchronous logic element, each branched synchronous logic element being synchronized using a crock signal of a respective clock domain of the integrated circuit;
synchronizing the first synchronous logic element using a first clock signal of the integrated circuit;
coupling an output of the first synchronous logic element to a data input of the at least one branched synchronous logic element; and
coupling an output of each of the at least one branched synchronous logic element with data inputs of synchronous logic elements of the respective clock domain;
the first and the at least one branched synchronous logic elements being reset in response to a reset signal applied to a data input of said first synchronous logic element.
2. The method of claim 1 wherein each synchronous logic element is a device having a clock input and at least one data input.
3. The method of claim 2 wherein each synchronous logic element is selected from the group consisting of a D-type flip-flop (D-FF). T-type flip-flop (T-FF), and a JK flip-flop.
4. The method of claim 1 wherein duration of the reset signal is substantially equal to or greater than a period of the slowest clock signal of the clock domain.
5. The method of claim 1 wherein said synchronous logic elements are edge-triggered devices.
6. The method of claim 1 wherein a data input of said branched synchronous logic element is coupled via an inverter.
7. The method of claim 1 wherein a data input of said synchronous logic element of the clock domain is coupled via an inverter.
8. A circuit configuration for synchronous resetting of a multiple clock domain integrated circuit, comprising:
a clocked reset tree comprising a first synchronous logic element, the first synchronous logic element being synchronized using a first clock signal of the integrated circuit; and
at least one branched synchronous logic element, each branched synchronous logic element being synchronized using a clock signal of a respective clock domain of the integrated circuit;
wherein an output of the first synchronous logic element is coupled to a data input of the at least one branched synchronous logic element and an output of each of the at least one branched synchronous logic element is coupled with data inputs of synchronous logic elements of the respective dock domain, the first and the at least one branched synchronous logic elements being reset in response to a reset signal applied to a data input of said first synchronous logic element.
9. The circuit configuration of claim 8 wherein each synchronous logic element is a device having a clock input and at least one data input.
10. The circuit configuration of claim 9 wherein each synchronous logic element is selected from the group consisting of a D-type flip-flop (D-FF), T-type flip-flop (T-FF), and a JK flip-flop.
11. The circuit configuration of claim 8 wherein duration of the reset signal is substantially equal to or greater than a period of the slowest clock signal.
12. The circuit configuration of claim 8 wherein said synchronous logic elements are edge-triggered devices.
13. The circuit configuration of claim 8 wherein a data input of said branched synchronous logic element is coupled via an inverter.
14. The circuit configuration of claim 8 wherein a data input of said synchronous logic element of the clock domain is coupled via an inverter.
15. A multiple clock domain integrated circuit, comprising:
at least one clock domain;
a source of a reset signal; and
a synchronous resetting circuit, comprising:
a clocked reset tree comprising a first synchronous logic element, the first synchronous logic element being synchronized using a first clock signal of the integrated circuit; and
at least one branched synchronous logic element, each branched synchronous logic element being synchronized using a clock signal of a respective clock domain of the integrated circuit;
wherein an output of the first synchronous logic element is coupled to a data input of the at least one branched Synchronous logic element and an output of each of the at least one branched synchronous logic element is coupled with data inputs of synchronous logic elements of the respective clock domain, the first and the at least one branched synchronous logic elements being reset in response to a reset signal applied to a data input of said first synchronous logic element.
16. The circuit of claim 15 wherein each synchronous logic element is device having a clock input and at least one data input.
17. The circuit of claim 16 wherein each synchronous logic element is selected from the group consisting of a D-type flip-flop (D-FF). T-type flip-flop (T-FF), and a JK flip-flop.
18. The circuit of claim 15 wherein duration of the reset signal is substantially equal to or greater than a period of the slowest clock signal.
19. The circuit of claim 15 wherein said synchronous logic elements are edge-triggered devices.
20. The circuit of claim 15 wherein a data input of said branched synchronous logic element is coupled via an inverter.
21. The circuit of claim 15 wherein a data input of said synchronous logic element of the clock domain is coupled via an inverter.