ECC encoding for uncorrectable errors
View Patent ↗An error detecting and correcting method and mechanism. An error correcting code for data is utilized wherein a special syndrome pattern is used to indicate corresponding data includes a previously detected uncorrectable error. In response to receiving data and corresponding first check bits from a storage device, new check bits corresponding to the read data are generated. Based upon the read check bits and newly generated check bits, a syndrome is generated. If an uncorrectable error is detected, the newly generated check bits are inverted prior to be stored. Subsequent readers of the stored data will generate a syndrome which corresponds to the predetermined pattern and determine that the data includes a previously detected uncorrectable error. Data including an error corresponding to an previously detected uncorrectable error may be discarded and no error reported.
1. A method comprising:
receiving data and corresponding first check bits from a storage device;
generating second check bits corresponding to the received data;
generating a first syndrome using the first check bits and the second check bits; and
inverting the second check bits and storing the second check bits, in response to determining the first syndrome indicates an uncorrectable error;
storing the received data in association with the inverted second check bits;
receiving the stored data and stored inverted second check bits;
generating third check bits corresponding to the retrieved stored data;
generating a second syndrome using the first check bits and the second check bits; and
determining the received stored data includes a previously detected uncorrectable error, in response to determining the second syndrome matches a predetermined syndrome.
2. The method as recited in claim 1 , further comprising:
detecting and correcting a single bit error corresponding to the stored data and second check bits, in response to determining the second syndrome indicates a single bit error; and
reporting an uncorrectable error in response to determining the second syndrome indicates an uncorrectable error.
3. The method as recited in claim 2 , wherein in response to determining the second syndrome matches a predetermined syndrome, an error corresponding to the previously detected uncorrected error is not reported.
4. The method as recited in claim 1 , wherein the first check bits are utilized to implement a single error correcting, double error detecting code.
5. The method as recited in claim 4 , wherein a first set of bits of the first syndrome are used to identify and correct an erroneous bit position in the retrieved data, in response to determining the second syndrome indicates a single bit error.
6. The method as recited in claim 5 , wherein in response to determining an odd number of bits of the syndrome are equal to the binary value “1” and the first set of bits represent a value greater than the number of bits in the retrieved data and first check bits combined, the first syndrome indicates an uncorrectable error.
7. An apparatus comprising:
one or more storage devices configured to store data and corresponding check bits; and
error correction circuitry coupled to receive data and check bits from the one or more storage devices;
wherein in response to receiving data and corresponding first check bits, the error correction circuitry is configured to:
generate second check bits corresponding to the received data;
generate a first syndrome using the first check bits and the second check bits; and
invert the second check bits and store the second check bits, in response to determining the first syndrome indicates an uncorrectable error;
wherein the received data is stored in association with the inverted second check bits, and
wherein the error correction circuitry is further configured to:
receive the stored data and stored inverted second check bits;
generate third check bits corresponding to the received stored data;
generate a second syndrome using the first check bits and the second check bits;
compare the second syndrome to a predetermined pattern; and
determine the received stored data includes a previously detected uncorrectable error, in response to determining the second syndrome matches a predetermined syndrome.
8. The apparatus as recited in claim 7 , wherein the error correction circuitry is further configured to:
detect and correct a single bit error corresponding to the stored data and second check bits, in response to determining the second syndrome indicates a single bit error; and
report an uncorrectable error in response to determining the second syndrome indicates an uncorrectable error.
9. The apparatus as recited in claim 8 , wherein in response to determining the second syndrome matches a predetermined syndrome, an error corresponding to the previously detected uncorrected error is not reported.
10. The apparatus as recited in claim 7 , wherein the error correction circuitry is configured to use the first check bits to implement a single error correcting, double error detecting code.
11. The apparatus as recited in claim 10 , wherein a first set of bits of the first syndrome are used to identify and correct an erroneous bit position in the retrieved data, in response to determining the second syndrome indicates a single bit error.
12. The apparatus as recited in claim 11 , wherein in response to determining an odd number of bits of the syndrome are equal to the binary value “1” and the first set of bits represent a value greater than the number of bits in the retrieved data and first check bits combined, the first syndrome indicates an uncorrectable error.
13. A computing system comprising:
one or more memory devices configured to store data and corresponding check bits; and
a processor coupled to access data in the one or more memory devices, wherein in response to receiving data and corresponding first check bits, the processor is configured to:
generate second check bits corresponding to the received data;
generate a first syndrome using the first check bits and the second check bits; and
invert the second check bits and store the second check bits, in response to determining the first syndrome indicates an uncorrectable error;
receive the data and stored inverted second check bits;
generate third check bits corresponding to the received data;
generate a second syndrome using the first check bits and the second check bits;
compare the second syndrome to a predetermined pattern; and
determine the received data includes a previously detected uncorrectable error, in response to determining the second syndrome matches a predetermined syndrome.
14. The computing system as recited in claim 13 , wherein the processor is further configured to:
detect and correct a single bit error corresponding to the stored data and second check bits, in response to determining the second syndrome indicates a single bit error; and
report an uncorrectable error in response to determining the second syndrome indicates an uncorrectable error.
15. The computing system as recited in claim 14 , wherein in response to determining the second syndrome matches a predetermined syndrome, an error corresponding to the previously detected uncorrected error is not reported.