IP Library Granted Patent US 7,250,665
Granted Patent B1
US 7,250,665 · App. 11/029,100 · Granted Jul 31, 2007

Method and apparatus for removing electrons from CMOS sensor photodetectors

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Quick Facts
Patent No.
US 7,250,665
App. No.
11/029,100
Granted
Jul 31, 2007
Kind
B1
Abstract

An improved CMOS sensor integrated circuit is disclosed, along with methods of making the circuit and computer readable descriptions of the circuit.

Claims (45)

1. An image sensor integrated circuit, comprising:

a plurality of oxide structures isolating adjacent photodetectors from each other;

a plurality of photodetectors generating electrons excited by incident photons, each of the plurality of photodetectors including:

a first n-type region receiving the electrons excited by the energy of the photons, the first n-type region at a first depth range in the integrated circuit;

a second n-type region at a second depth range wherein the first depth range includes depths deeper than the second depth range, the second n-type region positioned adjacent to the first n-type region and at least part of the second n-type region positioned between the first n-type region and an oxide structure of the plurality of oxide structures, and receiving the electrons from the first n-type region;

a plurality of nodes, wherein each of the plurality of photodetectors has a corresponding node of the plurality of nodes;

a plurality of transfer devices controlling a transfer of the electrons from the second region of said each of the plurality of photodetectors to the corresponding node, each of the plurality of transfer devices including:

a first terminal coupled to the second region of one of the plurality of photodetectors;

a second terminal coupled to one of the plurality of nodes; and

a control terminal receiving a control signal, wherein the transfer of the electrons between the first terminal and the second terminal occurs in response to the control signal of sufficient value applied to the control terminal;

a plurality of reset devices, wherein each of the plurality of nodes has a corresponding reset device of the plurality of reset devices, and said each of the plurality of nodes is reset when the corresponding reset device is active;

row and column circuitry; and

a plurality of signal devices coupling the plurality of nodes to the row and column circuitry.

2. The circuit of claim 1 , wherein a difference in n-type concentration between the first n-type region and the second n-type region causes electrons to move from the first n-type region to the second n-type region.

3. The circuit of claim 1 , wherein the second n-type region surrounds a perimeter of the first n-type region.

4. The circuit of claim 1 , wherein the second n-type region surrounds a perimeter of the first n-type region, and the second n-type region is formed with phosphorous implanted in an energy range of 80 to 120 keV and in a dose range of 1×10 12 to 6×10 12 atoms/cm 2 .

5. The circuit of claim 1 , wherein the second n-type region surrounds a perimeter of the first n-type region, and the first n-type region is formed with phosphorous implanted in an energy range of 280 to 320 kev and in a dose range of 8×10 11 to 1.4×10 12 atoms/cm 2 .

6. The circuit of claim 1 , further comprising:

a p-type region surrounding the first and second n-type regions, and a p-type doping of the p-type region has a higher concentration than an n-type doping of the first and second n-type regions.

7. The circuit of claim 1 , further comprising:

a plurality of p-type regions each surrounding the first and second n-type regions of a photodetector of the plurality of photodetectors, and a p-type doping of a p-type region of the plurality of p-type regions has a higher concentration than an n-type doping of the first and second n-type regions.

8. The circuit of claim 1 , further comprising:

a plurality of p-type regions each surrounding the first and second n-type regions of a photodetector of the plurality of photodetectors, and a p-type doping of a p-type region of the plurality of p-type regions has a higher concentration than an n-type doping of the first and second n-type regions, wherein the higher concentration assists depletion of the second n-type region.

9. The circuit of claim 1 , further comprising:

a plurality of p-type regions each surrounding the first and second n-type regions of a photodetector of the plurality of photodetectors, and a p-type doping of a p-type region of the plurality of p-type regions has a higher concentration than an n-type doping of the first and second n-type regions, wherein the p-type region isolates the first and second n-type regions from adjacent photodetectors.

10. The circuit of claim 1 , further comprising:

a plurality of p-type regions isolating neighboring photodetectors from each other.

11. The circuit of claim 1 , wherein each of the plurality of transfer devices includes a body connecting the first terminal and the second terminal such that the control terminal controls the transfer of the electrons between the first terminal and the second terminal through the body, and a dielectric between the control terminal and the body, the dielectric satisfying a lifetime specification of the image sensor integrated circuit when the control signal is applied with the channel formed, the dielectric failing the lifetime specification of the image sensor integrated circuit if the control signal is applied with at least one of the first terminal and the second terminal at a ground voltage of the image sensor integrated circuit.

12. The circuit of claim 1 , wherein the plurality of signal devices includes a plurality of row select transistors coupled to the row and column circuitry and a plurality of source follower transistors coupled to the plurality of nodes.

13. The circuit of claim 1 , wherein the plurality of photodetectors is a plurality of photodiodes.

14. The circuit of claim 1 , wherein each measurement of the total of the photons is corrected by correlated multiple sampling with a prior measurement of the total of the photons.

15. The circuit of claim 1 , wherein the plurality of oxide structures includes a plurality of pn junctions helping to isolate adjacent photodetectors from each other.

16. A computer readable description of an image sensor integrated circuit comprising:

a plurality of oxide structures isolating adjacent photodetectors from each other;

a plurality of photodetectors generating electrons excited by incident photons, each of the plurality of photodetectors including:

a first n-type region receiving the electrons excited by the energy of the photons, the first n-type region at a first depth range in the integrated circuit;

a second n-type region at a second depth range wherein the first depth range includes depths deeper than the second depth range, the second n-type region positioned adjacent to the first n-type region and at least part of the second n-type region positioned between the first n-type region and an oxide structure of the plurality of oxide structures, and receiving the electrons from the first n-type region;

a plurality of nodes, wherein each of the plurality of photodetectors has a corresponding node of the plurality of nodes;

a plurality of transfer devices controlling a transfer of the electrons from the second region of said each of the plurality of photodetectors to the corresponding node, each of the plurality of transfer devices including:

a first terminal coupled to the second region of one of the plurality of photodetectors;

a second terminal coupled to one of the plurality of nodes; and

a control terminal receiving a control signal, wherein the transfer of the electrons between the first terminal and the second terminal occurs in response to the control signal of sufficient value applied to the control terminal;

a plurality of reset devices, wherein each of the plurality of nodes has a corresponding reset device of the plurality of reset devices, and said each of the plurality of nodes is reset when the corresponding reset device is active;

row and column circuitry; and

a plurality of signal devices coupling the plurality of nodes to the row and column circuitry.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2022
From: PICTOS TECHNOLOGIES INC
To: RE SECURED NETWORKS LLC
Reel/Frame 060801/0001 →
CHANGE OF NAME Recorded Jun 15, 2021
From: IMPERIUM IP HOLDINGS (CAYMAN), LTD.
To: PICTOS TECHNOLOGIES INC.
Reel/Frame 056595/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2008
From: ESS TECHNOLOGY, INC.
To: IMPERIUM (IP) HOLDINGS
Reel/Frame 021316/0252 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 18, 2005
From: TOROS, ZEYNEP; MANN, RICHARD; BENCUYA, SELIM
To: ESS TECHNOLOGY, INC.
Reel/Frame 016473/0190 →