Method for designing a CMOS sensor using parameters

1. A method of designing with a simulation a CMOS image sensor integrated circuit having a photodetector using energy of photons reaching the photodetector to excite electrons; a transfer device with a first terminal coupled to the photodetector, a second terminal coupled to the corresponding node, and a control terminal causing a transfer of the electrons from the first terminal to the second terminal in response to receiving a control signal of sufficient value; a p-type region having a concentration stronger than a background concentration and having a lateral position at least partly under the control terminal of the transfer device; the simulation comprising:

selecting design parameters of a surface p-type region laterally positioned at the photodetector;

selecting design parameters of the transfer device;

selecting design parameters for a first n-type region and a second n-type region of the photodetector, the first n-type region at a first depth range in the integrated circuit and receiving the electrons excited by the photons, and the second n-type region at a second depth range wherein the first depth range includes depths deeper than the second depth range, the second n-type region being adjacent to the first n-type region and receiving the electrons from the first n-type region;

selecting design parameters of the p-type region;

filling the photodetector with electrons to a maximum capacity;

verifying that the maximum capacity of the photodetector meets a design specification of the integrated circuit; and

verifying that raising the control voltage on the control terminal, without exceeding a voltage tolerance of a dielectric, transfers the electrons from the photodetector to the corresponding node to be measured and removed.

2. The method of claim 1 , wherein the surface p-type region is self-aligned to the control terminal of the transfer device.

3. The method of claim 1 , wherein the surface p-type region pins a Fermi level of a surface of the photodetector.

4. The method of claim 1 , further comprising:

repeating said selecting design parameters of the surface p-type region, the transfer device, the first n-type region, the second n-type region, the p-type region, and said filling the photodetector with electrons to a maximum capacity, until said verifying of the maximum capacity of the photodetector is successful.

5. The method of claim 1 , further comprising:

repeating said selecting design parameters of the surface p-type region, the transfer device, the first n-type region, the second n-type region, the p-type region, and said filling the photodetector with electrons to a maximum capacity, until said verifying that raising the control voltage transfers the electrons is successful.

6. The method of claim 1 , further comprising:

shining the photons corresponding to multiple wavelengths on the photodetector; and

verifying sufficient isolation at the multiple wavelengths between the photodetector and a neighboring photodetector.

7. The method of claim 1 , wherein the plurality of signal devices includes a plurality of row select transistors coupled to the row and column circuitry and a plurality of source follower transistors coupled to the plurality of nodes.

8. The method of claim 1 , wherein the plurality of photodetectors is a plurality of photodiodes.

9. The method of claim 1 , wherein each measurement of the total of the photons is corrected by correlated multiple sampling with a prior measurement of the total of the photons.

10. A computer readable algorithm designing a CMOS image sensor integrated circuit having a photodetector using energy of photons reaching the photodetector to excite electrons; a transfer device with a first terminal coupled to the photodetector, a second terminal coupled to a corresponding node, and a control terminal causing a transfer of the electrons from the first terminal to the second terminal in response to receiving a control signal of sufficient value; a p-type region having a concentration stronger than a background concentration and having a lateral position at least partly under the control terminal of the transfer device; the computer readable algorithm performing:

selecting design parameters of a surface p-type region laterally positioned at the photodetector;

selecting design parameters of the transfer device;

selecting design parameters for a first n-type region and a second n-type region of the photodetector, the first n-type region at a first depth range in the integrated circuit and receiving the electrons excited by the photons, and the second n-type region at a second depth range wherein the first depth range includes depths deeper than the second depth range, the second n-type region being adjacent to the first n-type region, and receiving the electrons from the first n-type region;

selecting design parameters of the p-type region;

filling the photodetector with electrons to a maximum capacity;

verifying that the maximum capacity of the photodetector meets a design specification of the integrated circuit; and

verifying that raising the control voltage on the control terminal, without exceeding a voltage tolerance of a dielectric, transfers the electrons from the photodetector to the corresponding node to be measured and removed.

11. The computer readable algorithm of claim 10 , wherein the algorithm is carried by an electromagnetic waveform.

12. The computer readable algorithm of claim 10 , wherein the algorithm is carried by an optically accessed storage medium.

13. The computer readable algorithm of claim 10 , wherein the algorithm is carried by a magnetically accessed storage medium.

14. The computer readable algorithm of claim 10 , wherein the plurality of signal devices includes a plurality of row select transistors coupled to the row and column circuitry and a plurality of source follower transistors coupled to the plurality of nodes.

15. The computer readable algorithm of claim 10 , wherein the plurality of photodetectors is a plurality of photodiodes.

16. The computer readable algorithm of claim 10 , wherein each measurement of the total of the photons is corrected by correlated multiple sampling with a prior measurement of the total of the photons.

17. A set of masks for a CMOS image sensor integrated circuit having a photodetector using energy of photons reaching the photodetector to excite electrons; a transfer device with a first terminal coupled to the photodetector, a second terminal coupled to the corresponding node, and a control terminal causing a transfer of the electrons from the first terminal to the second terminal in response to receiving a control signal of sufficient value; a p-type region having a concentration stronger than a background concentration and having a lateral position at least partly under the control terminal of the transfer device; the set of masks designed by a simulation algorithm performing:

selecting design parameters of a surface p-type region laterally positioned at the photodetector;

selecting design parameters of the transfer device;

selecting design parameters for a first n-type region and a second n-type region of the photodetector, the first n-type region at a first depth range in the integrated circuit and receiving the electrons excited by the photons, and the second n-type region at a second depth range wherein the first depth range includes depths deeper than the second depth range, the second n-type region being adjacent to the first n-type region, and receiving the electrons from the first n-type region;

selecting design parameters of the p-type region;

filling the photodetector with electrons to a maximum capacity;

verifying that the maximum capacity of the photodetector meets a design specification of the integrated circuit; and

verifying that raising the control voltage on the control terminal, without exceeding a voltage tolerance of a dielectric, transfers the electrons from the photodetector to the corresponding node to be measured and removed.